公开(公告)号：US20220408550A1

公开(公告)日：2022-12-22

申请号：US17573156

申请日：2022-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongyoon SEO ,  Hwanwook PARK ,  Dohyung KIM ,  Bora KIM ,  Seungyeong LEE ,  Wonseop LEE ,  Yunho LEE ,  Yejin CHO

IPC: H05K1/02 ,  H05K1/11 ,  G11C11/4076

Abstract: A PCB includes a plurality of layers spaced apart in a vertical direction, a first detection pattern and a second detection pattern and pads connected to the first detection pattern and the second detection pattern. The first detection pattern and the second detection pattern are provided in a respective one of a first layer and a second layer adjacent to each other such that the first detection pattern and the second detection pattern are opposed to each other. The pads are provided in an outmost layer. Each of the first detection pattern and the second detection includes at least one main segment extending in at least one of first and second horizontal directions and a diagonal direction. A time domain reflectometry connected to a pair of pads detects a misalignment of the PCB by measuring differential characteristic impedance of the first detection pattern and the second detection pattern.

公开(公告)号：US20240324192A1

公开(公告)日：2024-09-26

申请号：US18613868

申请日：2024-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Young LEE ,  Shigenobu MAEDA ,  Kwan Young KIM ,  Bora KIM ,  Hoonjin BANG ,  Sangjin LEE

IPC: H10B20/25

CPC classification number: H10B20/25

Abstract: A one-time programmable (OTP) memory device includes: a semiconductor substrate having a write region and a read region; write gates disposed in the write region of the semiconductor substrate; read gates disposed in the read region of the semiconductor substrate; source/drain regions arranged adjacent to the write gates and the read gates and arranged in the semiconductor substrate; and a device isolation layer located between the write gates and arranged in the semiconductor substrate, wherein, in the semiconductor substrate, channel regions located below the write gates have a first conductivity type, wherein the source/drain regions have a second conductivity type, different from the first conductivity type, and wherein a pocket well is formed in the write region of the semiconductor substrate and has the second conductivity type.

公开(公告)号：US20230019282A1

公开(公告)日：2023-01-19

申请号：US17853148

申请日：2022-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoyoung SHIN ,  Bora KIM ,  Junho KIM

IPC: H03L7/099 ,  H03L7/107 ,  H03L7/081 ,  H03L7/083 ,  H03K19/173 ,  G06F7/58

Abstract: A random number generator includes a ring oscillator, an inversion selecting circuit, and controller. The ring oscillator includes an inverter chain having at least one inverter and generates an output signal. The inversion selecting circuit controlling a phase inverter configured to invert a signal of the inverter chain. The controller is configured to operate the inversion selecting circuit to provide an output of the first phase inverter to the inverter chain during a first operation mode to measure a frequency of the ring oscillator and operate the inversion selecting circuit to not provide the output of the phase inverter during a second operation mode for generating a random number.