公开(公告)号：US20160299690A1

公开(公告)日：2016-10-13

申请号：US15094454

申请日：2016-04-08

Applicant: SAMSUNG ELECTRONICS CO .. LTD.

Inventor： Gi Jo JUNG ,  Tae Hack LEE ,  Sang Kyoo JEONG ,  Kwang Ho CHOI ,  Myeong Eun HWANG

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0688

Abstract: A data storage device includes a processor and a non-volatile memory. The processor compares a data processing size of a first command received from the host at a first time point with a reference size and divides the first command into a plurality of sub-commands when the data processing size is greater than the reference size. The data storage device further includes a memory that includes a first queue and a second queue.

Abstract translation: 数据存储设备包括处理器和非易失性存储器。 处理器将在第一时间点从主机接收到的第一命令的数据处理大小与参考大小进行比较，并且当数据处理大小大于参考大小时，将第一命令划分为多个子命令。 数据存储装置还包括包括第一队列和第二队列的存储器。

公开(公告)号：US20140195726A1

公开(公告)日：2014-07-10

申请号：US14207974

申请日：2014-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Hack LEE

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0292

Abstract: A controller, a data storage device and a data storage system including the controller, and a data processing method are provided. The controller may process a plurality of instructions in parallel by including a plurality of address translation central processing units (CPUs) in a multi-channel parallel array structure, thereby improving the performance of a semiconductor memory system.

Abstract translation: 提供了一种控制器，数据存储设备和包括控制器的数据存储系统以及数据处理方法。 控制器可以通过在多通道并行阵列结构中包括多个地址转换中央处理单元（CPU）来并行处理多个指令，从而提高半导体存储器系统的性能。