公开(公告)号：US20170154585A1

公开(公告)日：2017-06-01

申请号：US15164042

申请日：2016-05-25

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： YongSoon LEE ,  Sang Hyun PARK ,  Kyungmo LEE ,  Yong-Sik HWANG

IPC: G09G3/36 ,  G09G3/20

CPC classification number: G09G3/36 ,  G09G3/2092 ,  G09G3/3677 ,  G09G2310/0205 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/08

Abstract: A display apparatus includes a timing controller configured to generate a single clock control signal comprising a plurality of ON-control pulses and a plurality of OFF-control pulses, a gate clock generator configured to generate a plurality of clock signals based on the single clock control signal, ON-periods of the plurality of clock signals starting in response to an ON-control pulse among the ON-control pulses and OFF-periods of the plurality of clock signals starting in response to an OFF-control pulse among the OFF-control pulses, a gate driver comprising a plurality of shift registers which generates a plurality of gate signals based on the plurality of clock signals, and a display panel comprising a display area in which a plurality of pixels is arranged and a peripheral area in which the plurality of shift registers is arranged.

公开(公告)号：US20180374432A1

公开(公告)日：2018-12-27

申请号：US16116240

申请日：2018-08-29

Applicant: SAMSUNG DISPLAY CO, LTD.

Inventor： YongSoon LEE ,  SANG HYUN PARK ,  KYUNGMO LEE ,  YONG-SIK HWANG

IPC: G09G3/36 ,  G09G3/20

CPC classification number: G09G3/36 ,  G09G3/2092 ,  G09G3/3677 ,  G09G2310/0205 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/08

Abstract: A display apparatus includes a timing controller configured to generate a single clock control signal comprising a plurality of ON-control pulses and a plurality of OFF-control pulses, a gate clock generator configured to generate a plurality of clock signals based on the single clock control signal, ON-periods of the plurality of clock signals starting in response to an ON-control pulse among the ON-control pulses and OFF-periods of the plurality of clock signals starting in response to an OFF-control pulse among the OFF-control pulses, a gate driver comprising a plurality of shift registers which generates a plurality of gate signals based on the plurality of clock signals, and a display panel comprising a display area in which a plurality of pixels is arranged and a peripheral area in which the plurality of shift registers is arranged.