公开(公告)号：US10852612B2

公开(公告)日：2020-12-01

申请号：US16733564

申请日：2020-01-03

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sangyong No ,  Kwihyun Kim ,  Jiho Moon ,  Keebum Park

IPC: G02F1/1368 ,  G02F1/1362 ,  G02F1/1343 ,  G02F1/1335 ,  G02F1/1333 ,  G02F1/133 ,  G02F1/1337

Abstract: A liquid crystal display device includes a liquid crystal layer between first and second substrate. The first substrate includes a first and second sub-pixel areas. A first sub-pixel electrode is on the first substrate in the first sub-pixel area, and a first transistor is connected to a gate line, data line, and first sub-pixel electrode on the first substrate. A second sub-pixel electrode is on the first substrate in the second sub-pixel area, and a second transistor is connected to the gate line, the first transistor, and the second sub-pixel electrode. A first storage line is adjacent to one side of the first sub-pixel electrode. A second storage line is spaced from the first storage line and is adjacent to one side of the second sub-pixel electrode. A third transistor is connected to the gate line, second transistor, and second storage line.

公开(公告)号：US10527901B2

公开(公告)日：2020-01-07

申请号：US15237673

申请日：2016-08-16

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sangyong No ,  Kwihyun Kim ,  Jiho Moon ,  Keebum Park

IPC: G02F1/1368 ,  G02F1/1362 ,  G02F1/1343 ,  G02F1/1335 ,  G02F1/1333 ,  G02F1/133 ,  G02F1/1337

Abstract: A liquid crystal display device includes a liquid crystal layer between first and second substrate. The first substrate includes a first and second sub-pixel areas. A first sub-pixel electrode is on the first substrate in the first sub-pixel area, and a first transistor is connected to a gate line, data line, and first sub-pixel electrode on the first substrate. A second sub-pixel electrode is on the first substrate in the second sub-pixel area, and a second transistor is connected to the gate line, the first transistor, and the second sub-pixel electrode. A first storage line is adjacent to one side of the first sub-pixel electrode. A second storage line is spaced from the first storage line and is adjacent to one side of the second sub-pixel electrode. A third transistor is connected to the gate line, second transistor, and second storage line.