公开(公告)号：US20140098926A1

公开(公告)日：2014-04-10

申请号：US14045700

申请日：2013-10-03

Applicant: Rohm Co., Ltd.

Inventor： Takaaki FUCHIKAMI ,  Noriyuki EMA ,  Hiromitsu KIMURA ,  Yoshikazu Fujimori

IPC: G06M1/10

CPC classification number: G06M1/10 ,  H03K21/023 ,  H03K21/12 ,  H03K21/38 ,  H03K21/403

Abstract: A counter includes: a count processing circuit including a nonvolatile register; a regulator receiving voltage from a direct current power supply, generating power supply voltage based on the received voltage for the count processing circuit, and supplying the power supply voltage to the count processing circuit; and a delay circuit receiving the power supply voltage and supplying a count signal to the count processing circuit after the power supply voltage is supplied to the count processing circuit. After having received the power supply voltage from the regulator, the count processing circuit updates a count value in response to the count signal and holds the updated count value in the nonvolatile register in a non-volatile manner.

Abstract translation: 计数器包括：包括非易失性寄存器的计数处理电路; 调节器，其从直流电源接收电压，基于所述计数处理电路的接收电压产生电源电压，并将所述电源电压提供给所述计数处理电路; 以及在向所述计数处理电路提供所述电源电压之后，接收所述电源电压并将计数信号提供给所述计数处理电路的延迟电路。 在从调节器接收到电源电压之后，计数处理电路响应于计数信号更新计数值，并以非易失性的方式将更新的计数值保持在非易失性寄存器中。

公开(公告)号：US20240170084A1

公开(公告)日：2024-05-23

申请号：US18427383

申请日：2024-01-30

Applicant: Rohm Co., Ltd.

Inventor： Hiromitsu KIMURA ,  Tomokazu Okada ,  Yuji KUROTSUCHI

IPC: G11C29/12 ,  B60W50/04

CPC classification number: G11C29/1201 ,  B60W50/04 ,  B60W2050/041

Abstract: A semiconductor device includes, for example, internal circuitry (for example, a CPU), external terminals (for example, debug control terminals of the CPU) configured to be used by the internal circuitry in a non-test mode (for example, a debug mode of the CPU), and a test circuit configured to, upon detecting that a particular dedicated test mode control pattern has been inputted to the external terminals, cause a transition from the non-test mode to a test mode.

公开(公告)号：US20240119215A1

公开(公告)日：2024-04-11

申请号：US18545662

申请日：2023-12-19

Applicant: ROHM CO., LTD.

Inventor： Kenichi YOSHIMURA ,  Hiromitsu KIMURA ,  Tomokazu OKADA ,  Yuji KUROTSUCHI

IPC: G06F30/3953 ,  G06F30/38 ,  G06F30/392

CPC classification number: G06F30/3953 ,  G06F30/38 ,  G06F30/392 ,  G06F2111/20

Abstract: For example, an I/O circuit is formed by freely combining a plurality of kinds of standard cells included in a cell library. The plurality of kinds of standard cells include at least first standard cells and a second standard cell. The first standard cells include first protection elements and a first power line formed in a region over the first protection elements to conduct to the first protection elements. The second standard cell includes a second protection element formed in a layout identical with that of the first protection elements, and a second power line formed in a region over the second protection element to conduct to the second protection element while being isolated from the first power line.