公开(公告)号：US20140061847A1

公开(公告)日：2014-03-06

申请号：US14073754

申请日：2013-11-06

Applicant: Renesas Electronics Corporation

Inventor： Kunihiko Kato ,  Hideki Yasuoka ,  Masatoshi Taya ,  Masami Koketsu

IPC: H01L29/872

CPC classification number: H01L29/872 ,  H01L27/0629 ,  H01L29/0692 ,  H01L29/417

Abstract: The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.

Abstract translation: 本发明旨在提高在同一芯片内配备肖特基势垒二极管的半导体器件及其制造技术的可靠性。 半导体器件包括在p型半导体衬底上形成的n型n阱区，部分形成并且杂质浓度高于n阱区的n型阴极区，p型保护环区 形成为包围n型阴极区域的阳极导体膜，形成为一体地覆盖n型阴极区域和p型保护环区域并与其电耦合，形成n型阴极导电区域 在其间留有各个分离部分的p型保护环区域外部，以及形成为覆盖n型阴极导电区域并与其电耦合的阴极导体膜。 阳极导体膜和n型阴极区彼此肖特基耦合。

公开(公告)号：US08860169B2

公开(公告)日：2014-10-14

申请号：US14073754

申请日：2013-11-06

Applicant: Renesas Electronics Corporation

Inventor： Kunihiko Kato ,  Hideki Yasuoka ,  Masatoshi Taya ,  Masami Koketsu

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/872 ,  H01L27/06

CPC classification number: H01L29/872 ,  H01L27/0629 ,  H01L29/0692 ,  H01L29/417

Abstract: The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other.

Abstract translation: 本发明旨在提高在同一芯片内配备肖特基势垒二极管的半导体器件及其制造技术的可靠性。 半导体器件包括在p型半导体衬底上形成的n型n阱区，部分形成并且杂质浓度高于n阱区的n型阴极区，p型保护环区 形成为包围n型阴极区域的阳极导体膜，形成为一体地覆盖n型阴极区域和p型保护环区域并与其电耦合，形成n型阴极导电区域 在其间留有各个分离部分的p型保护环区域外部，以及形成为覆盖n型阴极导电区域并与其电耦合的阴极导体膜。 阳极导体膜和n型阴极区彼此肖特基耦合。