Semiconductor device and method for generating test pulse signals

    公开(公告)号:US12105144B2

    公开(公告)日:2024-10-01

    申请号:US17730243

    申请日:2022-04-27

    IPC分类号: G01R31/317 G06F1/10

    CPC分类号: G01R31/31726 G06F1/10

    摘要: A semiconductor device includes a control signal generating circuit, a first circuit and a second circuit. The control signal generating circuit is configured to generate a control signal. The first circuit is coupled to the control signal generating circuit and configured to receive the control signal and generate a first test pulse signal according to the control signal. The second circuit is coupled to the control signal generating circuit and the first circuit and configured to receive the control signal and generate a second test pulse signal according to the control signal. The first circuit is comprised in the first block. The second circuit is comprised in the second block. The first block and the second block are connected with each other via one or more interconnection logics and timing of the first test pulse signal and timing of the second test pulse signal are synchronized.

    Semiconductor device and method for generating test pulse signals

    公开(公告)号:US20220413044A1

    公开(公告)日:2022-12-29

    申请号:US17730243

    申请日:2022-04-27

    IPC分类号: G01R31/317 G06F1/10

    摘要: A semiconductor device includes a control signal generating circuit, a first circuit and a second circuit. The control signal generating circuit is configured to generate a control signal. The first circuit is coupled to the control signal generating circuit and configured to receive the control signal and generate a first test pulse signal according to the control signal. The second circuit is coupled to the control signal generating circuit and the first circuit and configured to receive the control signal and generate a second test pulse signal according to the control signal. The first circuit is comprised in the first block. The second circuit is comprised in the second block. The first block and the second block are connected with each other via one or more interconnection logics and timing of the first test pulse signal and timing of the second test pulse signal are synchronized.