公开(公告)号：US11468332B2

公开(公告)日：2022-10-11

申请号：US15810946

申请日：2017-11-13

Applicant: Raytheon Company

Inventor： John R. Goulding ,  John E. Mixter ,  David R. Mucha ,  Troy A. Gangwer ,  Ryan D. Silva

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: Processing circuitry for a deep neural network can include input/output ports, and a plurality of neural network layers coupled in order from a first layer to a last layer, each of the plurality of neural network layers including a plurality of weighted computational units having circuitry to interleave forward propagation of computational unit input values from the first layer to the last layer and backward propagation of output error values from the last layer to the first layer.

公开(公告)号：US20190147342A1

公开(公告)日：2019-05-16

申请号：US15810946

申请日：2017-11-13

Applicant: Raytheon Company

Inventor： John R. Goulding ,  John E. Mixter ,  David R. Mucha ,  Troy A. Gangwer ,  Ryan D. Silva

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: Processing circuitry for a deep neural network can include input/output ports, and a plurality of neural network layers coupled in order from a first layer to a last layer, each of the plurality of neural network layers including a plurality of weighted computational units having circuitry to interleave forward propagation of computational unit input values from the first layer to the last layer and backward propagation of output error values from the last layer to the first layer.