公开(公告)号：US11475311B2

公开(公告)日：2022-10-18

申请号：US16668957

申请日：2019-10-30

Applicant: Raytheon Company

Inventor： John E. Mixter ,  David R. Mucha

IPC: G06N3/08 ,  G06F9/38 ,  G06N3/04

Abstract: An artificial neural network is implemented via an instruction stream. A header of the instruction stream and a format for instructions in the instruction stream are defined. The format includes an opcode, an address, and data. The instruction stream is created using the header, the opcode, the address, and the data. The artificial neural network is implemented by providing the instruction stream to a computer processor for execution of the instruction stream.

公开(公告)号：US11468332B2

公开(公告)日：2022-10-11

申请号：US15810946

申请日：2017-11-13

Applicant: Raytheon Company

Inventor： John R. Goulding ,  John E. Mixter ,  David R. Mucha ,  Troy A. Gangwer ,  Ryan D. Silva

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: Processing circuitry for a deep neural network can include input/output ports, and a plurality of neural network layers coupled in order from a first layer to a last layer, each of the plurality of neural network layers including a plurality of weighted computational units having circuitry to interleave forward propagation of computational unit input values from the first layer to the last layer and backward propagation of output error values from the last layer to the first layer.

公开(公告)号：US20190087708A1

公开(公告)日：2019-03-21

申请号：US15711457

申请日：2017-09-21

Applicant: Raytheon Company

Inventor： John R. Goulding ,  John E. Mixter ,  David R. Mucha

IPC: G06N3/04 ,  G06F12/0817

Abstract: A dynamically adaptive neural network processing system includes memory to store instructions representing a neural network in contiguous blocks, hardware acceleration (HA) circuitry to execute the neural network, direct memory access (DMA) circuitry to transfer the instructions from the contiguous blocks of the memory to the HA circuitry, and a central processing unit (CPU) to dynamically modify a linked list representing the neural network during execution of the neural network by the HA circuitry to perform machine learning, and to generate the instructions in the contiguous blocks of the memory based on the linked list.

公开(公告)号：US20210133579A1

公开(公告)日：2021-05-06

申请号：US16668957

申请日：2019-10-30

Applicant: Raytheon Company

Inventor： John E. Mixter ,  David R. Mucha

IPC: G06N3/08 ,  G06N3/04 ,  G06F9/38

Abstract: An artificial neural network is implemented via an instruction stream. A header of the instruction stream and a format for instructions in the instruction stream are defined. The format includes an opcode, an address, and data. The instruction stream is created using the header, the opcode, the address, and the data. The artificial neural network is implemented by providing the instruction stream to a computer processor for execution of the instruction stream.

公开(公告)号：US20190147342A1

公开(公告)日：2019-05-16

申请号：US15810946

申请日：2017-11-13

Applicant: Raytheon Company

Inventor： John R. Goulding ,  John E. Mixter ,  David R. Mucha ,  Troy A. Gangwer ,  Ryan D. Silva

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: Processing circuitry for a deep neural network can include input/output ports, and a plurality of neural network layers coupled in order from a first layer to a last layer, each of the plurality of neural network layers including a plurality of weighted computational units having circuitry to interleave forward propagation of computational unit input values from the first layer to the last layer and backward propagation of output error values from the last layer to the first layer.