公开(公告)号：US20150378639A1

公开(公告)日：2015-12-31

申请号：US14318874

申请日：2014-06-30

Applicant: Raytheon Company

Inventor： Pen C. Chien ,  Frank N. Cheung ,  Kuan Y. Huang

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0604 ,  G06F3/0673 ,  G06F15/167

Abstract: Embodiments relate to an inter-processor memory. An aspect includes a plurality of memory banks, each of the plurality of memory banks comprising a respective plurality of parallel memory modules, wherein a number of the plurality of memory banks is equal to a number of read ports of the inter-processor memory, and a number of parallel memory modules within a memory bank is equal to a number of write ports of the inter-processor memory. Another aspect includes each memory bank corresponding to a single respective read port of the inter-processor memory, and wherein, within each memory bank, each memory module of the plurality of parallel memory modules is writable in parallel by a single respective write port of the inter-processor memory.

Abstract translation: 实施例涉及处理器间存储器。 一个方面包括多个存储器组，多个存储体组中的每一个包括相应的多个并行存储器模块，其中多个存储器组中的多个等于处理器间存储器的读取端口的数量，以及 存储器组内的多个并行存储器模块等于处理器间存储器的多个写入端口。 另一方面包括对应于处理器间存储器的单个相应读取端口的每个存储器组，并且其中在每个存储器组内，多个并行存储器模块中的每个存储器模块可由并行存储的单个相应的写入端口 处理器间内存

公开(公告)号：US09335947B2

公开(公告)日：2016-05-10

申请号：US14318874

申请日：2014-06-30

Applicant: Raytheon Company

Inventor： Pen C. Chien ,  Frank N. Cheung ,  Kuan Y. Huang

IPC: G06F13/00 ,  G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0604 ,  G06F3/0673 ,  G06F15/167

Abstract: Embodiments relate to an inter-processor memory. An aspect includes a plurality of memory banks, each of the plurality of memory banks comprising a respective plurality of parallel memory modules, wherein a number of the plurality of memory banks is equal to a number of read ports of the inter-processor memory, and a number of parallel memory modules within a memory bank is equal to a number of write ports of the inter-processor memory. Another aspect includes each memory bank corresponding to a single respective read port of the inter-processor memory, and wherein, within each memory bank, each memory module of the plurality of parallel memory modules is writable in parallel by a single respective write port of the inter-processor memory.

Abstract translation: 实施例涉及处理器间存储器。 一个方面包括多个存储器组，多个存储体组中的每一个包括相应的多个并行存储器模块，其中多个存储器组中的多个等于处理器间存储器的读取端口的数量，以及 存储器组内的多个并行存储器模块等于处理器间存储器的多个写入端口。 另一方面包括对应于处理器间存储器的单个相应读取端口的每个存储器组，并且其中在每个存储器组内，多个并行存储器模块中的每个存储器模块可由并行存储的单个相应的写入端口 处理器间内存