公开(公告)号：US20150378639A1

公开(公告)日：2015-12-31

申请号：US14318874

申请日：2014-06-30

Applicant: Raytheon Company

Inventor： Pen C. Chien ,  Frank N. Cheung ,  Kuan Y. Huang

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0604 ,  G06F3/0673 ,  G06F15/167

Abstract: Embodiments relate to an inter-processor memory. An aspect includes a plurality of memory banks, each of the plurality of memory banks comprising a respective plurality of parallel memory modules, wherein a number of the plurality of memory banks is equal to a number of read ports of the inter-processor memory, and a number of parallel memory modules within a memory bank is equal to a number of write ports of the inter-processor memory. Another aspect includes each memory bank corresponding to a single respective read port of the inter-processor memory, and wherein, within each memory bank, each memory module of the plurality of parallel memory modules is writable in parallel by a single respective write port of the inter-processor memory.

Abstract translation: 实施例涉及处理器间存储器。 一个方面包括多个存储器组，多个存储体组中的每一个包括相应的多个并行存储器模块，其中多个存储器组中的多个等于处理器间存储器的读取端口的数量，以及 存储器组内的多个并行存储器模块等于处理器间存储器的多个写入端口。 另一方面包括对应于处理器间存储器的单个相应读取端口的每个存储器组，并且其中在每个存储器组内，多个并行存储器模块中的每个存储器模块可由并行存储的单个相应的写入端口 处理器间内存

公开(公告)号：US09335947B2

公开(公告)日：2016-05-10

申请号：US14318874

申请日：2014-06-30

Applicant: Raytheon Company

Inventor： Pen C. Chien ,  Frank N. Cheung ,  Kuan Y. Huang

IPC: G06F13/00 ,  G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0604 ,  G06F3/0673 ,  G06F15/167

Abstract: Embodiments relate to an inter-processor memory. An aspect includes a plurality of memory banks, each of the plurality of memory banks comprising a respective plurality of parallel memory modules, wherein a number of the plurality of memory banks is equal to a number of read ports of the inter-processor memory, and a number of parallel memory modules within a memory bank is equal to a number of write ports of the inter-processor memory. Another aspect includes each memory bank corresponding to a single respective read port of the inter-processor memory, and wherein, within each memory bank, each memory module of the plurality of parallel memory modules is writable in parallel by a single respective write port of the inter-processor memory.

Abstract translation: 实施例涉及处理器间存储器。 一个方面包括多个存储器组，多个存储体组中的每一个包括相应的多个并行存储器模块，其中多个存储器组中的多个等于处理器间存储器的读取端口的数量，以及 存储器组内的多个并行存储器模块等于处理器间存储器的多个写入端口。 另一方面包括对应于处理器间存储器的单个相应读取端口的每个存储器组，并且其中在每个存储器组内，多个并行存储器模块中的每个存储器模块可由并行存储的单个相应的写入端口 处理器间内存

公开(公告)号：US20160055035A1

公开(公告)日：2016-02-25

申请号：US14640338

申请日：2015-03-06

Applicant: Raytheon Company

Inventor： Ray T. Hsu ,  Harry B. Marr ,  Frank N. Cheung

IPC: G06F9/50

CPC classification number: G06F9/5027 ,  G06F2209/5021

Abstract: A method for scheduling a plurality of resources for processing a plurality of requests is provided. The method sorts the requests, each specifying a priority and one or more resources that process the request, in parallel based on the priorities. The method initializes an output set to an empty set and filters out any request that has a resource conflict with a current highest priority request, adds the current highest priority request to the output set and determines whether one or more requests of the plurality of requests, other than the requests added to the output set, are not filtered out. Responsive to determining that the one or more requests are not filtered out, repeating filtering, adding, and determining by using a highest priority request of the one or more requests as a current highest priority request. The method causes the assigned resources to process the output set of requests in parallel.

Abstract translation: 提供了一种用于调度用于处理多个请求的多个资源的方法。 该方法根据优先级并行排序请求，每个请求均指定优先级和一个或多个处理请求的资源。 该方法将输出集初始化为空集合，并且过滤掉与当前最高优先级请求资源冲突的任何请求，将当前最高优先级请求添加到输出集合，并确定多个请求中的一个或多个请求， 除了添加到输出集的请求之外，不会过滤掉。 响应于确定所述一个或多个请求不被过滤掉，通过使用所述一个或多个请求的最高优先级请求作为当前最高优先级请求来重复过滤，添加和确定。 该方法使分配的资源并行处理请求的输出集合。