公开(公告)号：US20170083707A1

公开(公告)日：2017-03-23

申请号：US15369299

申请日：2016-12-05

Applicant: Raytheon Company

Inventor： Brandon Woolley ,  Norman Cramer ,  Brian McFarland ,  Matthew Hammond

IPC: G06F21/57 ,  G06F1/24 ,  G06F9/44

CPC classification number: G06F21/572 ,  G06F1/24 ,  G06F9/4401 ,  G06F9/4405 ,  G06F9/4418 ,  G06F9/44505 ,  G06F15/177 ,  G06F21/57 ,  G06F21/575

Abstract: A system and methods are disclosed for securely booting a processing system using a three step secure booting process. Several embodiments are presented, wherein upon power-on-reset, the first boot step uses a secure boot device comprising of a programmable device or an FPGA which boots up first, validates its configuration file and then validates the processor(s) configuration data before presenting the configuration data to the processor(s). This enables validation of ‘pre-boot’ information, such as the Reset Control Word and pre-boot processor configuration data. The second and third boot steps validate the internal secure boot code and external boot code respectively using one or more of secure validation techniques, such as encryption/decryption, Key mechanisms, privilege checking, pointer hashing or signature correlation schemes. This results in an end-to-end secure boot process for a variety of architectures, such as single processor systems, synchronous and asynchronous multiprocessing systems, single core systems and multi-core processing systems.

公开(公告)号：US10121006B2

公开(公告)日：2018-11-06

申请号：US15369299

申请日：2016-12-05

Applicant: Raytheon Company

Inventor： Brandon Woolley ,  Norman Cramer ,  Brian McFarland ,  Matthew Hammond

IPC: G06F21/57 ,  G06F9/4401 ,  G06F9/445 ,  G06F1/24 ,  G06F15/177

Abstract: A system and methods are disclosed for securely booting a processing system using a three step secure booting process. Several embodiments are presented, wherein upon power-on-reset, the first boot step uses a secure boot device comprising of a programmable device or an FPGA which boots up first, validates its configuration file and then validates the processor(s) configuration data before presenting the configuration data to the processor(s). This enables validation of ‘pre-boot’ information, such as the Reset Control Word and pre-boot processor configuration data. The second and third boot steps validate the internal secure boot code and external boot code respectively using one or more of secure validation techniques, such as encryption/decryption, Key mechanisms, privilege checking, pointer hashing or signature correlation schemes. This results in an end-to-end secure boot process for a variety of architectures, such as single processor systems, synchronous and asynchronous multiprocessing systems, single core systems and multi-core processing systems.

公开(公告)号：US09536094B2

公开(公告)日：2017-01-03

申请号：US14154015

申请日：2014-01-13

Applicant: Raytheon Company

Inventor： Brandon Woolley ,  Norman Cramer ,  Brian Mcfarland ,  Matthew Hammond

IPC: G06F9/24 ,  G06F15/177 ,  G06F1/24 ,  G06F11/00 ,  G06F12/14 ,  G06F21/57 ,  G06F9/445 ,  G06F9/44

CPC classification number: G06F21/572 ,  G06F1/24 ,  G06F9/4401 ,  G06F9/4405 ,  G06F9/4418 ,  G06F9/44505 ,  G06F15/177 ,  G06F21/57 ,  G06F21/575

Abstract: A system and methods are disclosed for securely booting a processing system using a three step secure booting process. Several embodiments are presented, wherein upon power-on-reset, the first boot step uses a secure boot device comprising of a programmable device or an FPGA which boots up first, validates its configuration file and then validates the processor(s) configuration data before presenting the configuration data to the processor(s). This enables validation of ‘pre-boot’ information, such as the Reset Control Word and pre-boot processor configuration data. The second and third boot steps validate the internal secure boot code and external boot code respectively using one or more of secure validation techniques, such as encryption/decryption, Key mechanisms, privilege checking, pointer hashing or signature correlation schemes. This results in an end-to-end secure boot process for a variety of architectures, such as single processor systems, synchronous and asynchronous multiprocessing systems, single core systems and multi-core processing systems.

Abstract translation: 公开了一种使用三步安全启动过程安全地引导处理系统的系统和方法。 提出了几个实施例，其中在上电复位时，第一启动步骤使用包括可编程设备或FPGA的安全引导设备，其首先启动，验证其配置文件，然后在之前验证处理器配置数据 将配置数据呈现给处理器。 这样可以验证“预引导”信息，例如复位控制字和预引导处理器配置数据。 第二和第三启动步骤分别使用一种或多种安全验证技术来验证内部安全引导代码和外部引导代码，例如加密/解密，密钥机制，特权检查，指针散列或签名相关方案。 这导致用于各种架构的端到端安全引导过程，例如单处理器系统，同步和异步多处理系统，单核系统和多核处理系统。

公开(公告)号：US20150199520A1

公开(公告)日：2015-07-16

申请号：US14154015

申请日：2014-01-13

Applicant: Raytheon Company

Inventor： Brandon Woolley ,  Norman Cramer ,  Brian Mcfarland ,  Matthew Hammond

IPC: G06F21/57

CPC classification number: G06F21/572 ,  G06F1/24 ,  G06F9/4401 ,  G06F9/4405 ,  G06F9/4418 ,  G06F9/44505 ,  G06F15/177 ,  G06F21/57 ,  G06F21/575

Abstract: A system and methods are disclosed for securely booting a processing system using a three step secure booting process. Several embodiments are presented, wherein upon power-on-reset, the first boot step uses a secure boot device comprising of a programmable device or an FPGA which boots up first, validates its configuration file and then validates the processor(s) configuration data before presenting the configuration data to the processor(s). This enables validation of ‘pre-boot’ information, such as the Reset Control Word and pre-boot processor configuration data. The second and third boot steps validate the internal secure boot code and external boot code respectively using one or more of secure validation techniques, such as encryption/decryption, Key mechanisms, privilege checking, pointer hashing or signature correlation schemes. This results in an end-to-end secure boot process for a variety of architectures, such as single processor systems, synchronous and asynchronous multiprocessing systems, single core systems and multi-core processing systems.

Abstract translation: 公开了一种使用三步安全启动过程安全地引导处理系统的系统和方法。 提出了几个实施例，其中在上电复位时，第一启动步骤使用包括可编程设备或FPGA的安全引导设备，其首先启动，验证其配置文件，然后在之前验证处理器配置数据 将配置数据呈现给处理器。 这样可以验证“预引导”信息，例如复位控制字和预引导处理器配置数据。 第二和第三启动步骤分别使用一种或多种安全验证技术（例如加密/解密，密钥机制，特权检查，指针散列或签名相关方案）来验证内部安全引导代码和外部引导代码。 这导致用于各种架构的端到端安全引导过程，例如单处理器系统，同步和异步多处理系统，单核系统和多核处理系统。