公开(公告)号：US20250055472A1

公开(公告)日：2025-02-13

申请号：US18799138

申请日：2024-08-09

Applicant: Renesas Electronics Corporation

Inventor： Tomohiko EBATA ,  Tetsuo MATSUI

IPC: H03M1/46 ,  H03M1/12 ,  H03M1/14

Abstract: A semiconductor device is provided. The semiconductor device is capable of operating accurately by suppressing errors caused by dielectric relaxation phenomena. The semiconductor device includes a first capacitive element, a signal cancellation circuit, a sampling circuit, a negative feedback circuit, an AD converter, and an addition-and-subtraction circuit.

公开(公告)号：US20250055471A1

公开(公告)日：2025-02-13

申请号：US18798978

申请日：2024-08-09

Applicant: Renesas Electronics Corporation

Inventor： Tomohiko EBATA ,  Tetsuo MATSUI

IPC: H03M1/46 ,  H03M1/12

Abstract: A semiconductor device is provided. The semiconductor device is capable of operating accurately by suppressing errors caused by dielectric relaxation phenomena. The semiconductor device includes a first capacitive element, a first switch circuit, a first inversion signal generating circuit, a second capacitive element, and a negative feedback circuit.

公开(公告)号：US20220166443A1

公开(公告)日：2022-05-26

申请号：US17529885

申请日：2021-11-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomohiko EBATA

IPC: H03M1/46 ,  H03M1/12

Abstract: A semiconductor device performs sequential comparison of an analog input signal and a reference voltage to digitally convert the analog input signal. The semiconductor device includes an upper DAC generating a high-voltage region of the reference voltage based on a predetermined code, a lower DAC generating a low-voltage region of the reference voltage based on the code, and an injection DAC having the same configuration as that of the lower DAC and adjusting the low-voltage region of the reference voltage.

公开(公告)号：US20140085121A1

公开(公告)日：2014-03-27

申请号：US14023642

申请日：2013-09-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomohiko EBATA ,  Takuji ASO

IPC: H03M1/12

CPC classification number: H03M1/1076 ,  H03M1/12 ,  H03M1/1225

Abstract: The semiconductor integrated circuit device includes a T-type switch circuit TS[k] that is between an input port A[k] and an input terminal Ain of an analog/digital conversion circuit and that includes first, second, and third PMOS transistors MP1, MP2, and MPc, and first, second, and third NMOS transistors MN1, MN2, and MNc; and a fourth PMOS transistor MPu for pre-charging the input terminal Ain to a power supply voltage VCCA. In detecting the presence or absence of a disconnection from the input port A[k] to a signal input terminal Vint[k], first, the input terminal Ain is pre-charged to the power supply voltage VCCA via the fourth PMOS transistor MPu and also the second NMOS transistor MN2 and the second PMOS transistor MP2 are turned on, and the first NMOS transistor MN1, the first PMOS transistor MP1, the third PMOS transistor MPc, and third the NMOS transistor MNc are turned off.

Abstract translation: 半导体集成电路器件包括在模拟/数字转换电路的输入端口A [k]和输入端子Ain之间的T型开关电路TS [k]，并且包括第一，第二和第三PMOS晶体管MP1 ，MP2和MPc以及第一，第二和第三NMOS晶体管MN1，MN2和MNc; 以及用于将输入端子Ain预充电到电源电压VCCA的第四PMOS晶体管MPu。 在检测到从输入端口A [k]到信号输入端子Vint [k]的断开的存在或不存在时，首先，输入端子Ain经由第四PMOS晶体管MPu预充电到电源电压VCCA， 第二NMOS晶体管MN2和第二PMOS晶体管MP2也被导通，并且第一NMOS晶体管MN1，第一PMOS晶体管MP1，第三PMOS晶体管MPc和第三NMOS晶体管MNc截止。

公开(公告)号：US20200212925A1

公开(公告)日：2020-07-02

申请号：US16717070

申请日：2019-12-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuo MATSUI ,  Keisaku SENTO ,  Tomohiko EBATA

IPC: H03M1/46 ,  H03M1/12

Abstract: A conventional analog-to-digital conversion circuit has a problem that conversion errors cannot be suppressed. According to one embodiment, the analog-to-digital conversion circuit includes a first digital-to-analog conversion circuit 30 of a capacitance distribution type, a second digital-to-analog conversion circuit 31 of a capacitance distribution type, and a comparison circuit 32 for comparing output voltages of the two digital-to-analog conversion circuits, and before performing a successive comparison operation for successively changing a reference voltage applied to the first digital-to-analog conversion circuit, generates an intermediate digital value having a digital value corresponding to a voltage value of an analog input signal, determines a reference voltage to be applied to the second digital-to-analog conversion circuit 31 in accordance with the intermediate digital value, and thereafter performs a successive comparison operation using the first digital-to-analog conversion circuit 30 in a state in which the state of the second digital-to-analog conversion circuit 31 is held.

公开(公告)号：US20150194977A1

公开(公告)日：2015-07-09

申请号：US14666406

申请日：2015-03-24

Applicant: Renesas Electronics Corporation

Inventor： Tomohiko EBATA ,  Takuji ASO

IPC: H03M1/10 ,  H03M1/12

CPC classification number: H03M1/1076 ,  H03M1/12 ,  H03M1/1225

Abstract: The semiconductor integrated circuit device includes a T-type switch circuit TS[k] that is between an input port A[k] and an input terminal Ain of an analog/digital conversion circuit and that includes first, second, and third PMOS transistors MP1, MP2, and MPc, and first, second, and third NMOS transistors MN1, MN2, and MNc; and a fourth PMOS transistor MPu for pre-charging the input terminal Ain to a power supply voltage VCCA. In detecting the presence or absence of a disconnection from the input port A[k] to a signal input terminal Vint[k], first, the input terminal Ain is pre-charged to the power supply voltage VCCA via the fourth PMOS transistor MPu and also the second NMOS transistor MN2 and the second PMOS transistor MP2 are turned on, and the first NMOS transistor MN1, the first PMOS transistor MP1, the third PMOS transistor MPc, and third the NMOS transistor MNc are turned off.

Abstract translation: 半导体集成电路器件包括在模拟/数字转换电路的输入端口A [k]和输入端子Ain之间的T型开关电路TS [k]，并且包括第一，第二和第三PMOS晶体管MP1 ，MP2和MPc以及第一，第二和第三NMOS晶体管MN1，MN2和MNc; 以及用于将输入端子Ain预充电到电源电压VCCA的第四PMOS晶体管MPu。 在检测到从输入端口A [k]到信号输入端子Vint [k]的断开的存在或不存在时，首先，输入端子Ain经由第四PMOS晶体管MPu预充电到电源电压VCCA， 第二NMOS晶体管MN2和第二PMOS晶体管MP2也被导通，并且第一NMOS晶体管MN1，第一PMOS晶体管MP1，第三PMOS晶体管MPc和第三NMOS晶体管MNc截止。