公开(公告)号：US20170092718A1

公开(公告)日：2017-03-30

申请号：US15374263

申请日：2016-12-09

Applicant: Renesas Electronics Corporation

Inventor： Tatsunori MURATA ,  Takahiro MARUYAMA

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L21/764

CPC classification number: H01L29/0649 ,  H01L21/02107 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/76224 ,  H01L21/764

Abstract: An object of the invention is to provide a semiconductor device having improved performance. A method of manufacturing a semiconductor device includes: forming a trench and then forming a first insulating film made of a silicon oxide film through CVD using a gas containing an O3 gas and a TEOS gas to cover the side surface of the trench with the insulating film; forming a second insulating film made of a silicon oxide film through PECVD to cover the side surface of the trench with the second insulating film via the first insulating film; and forming a third insulating film made of a silicon oxide film through CVD using a gas containing an O3 gas and a TEOS gas to close the trench with the third insulating film while leaving a space in the trench.

公开(公告)号：US20160133507A1

公开(公告)日：2016-05-12

申请号：US14988013

申请日：2016-01-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsunori MURATA ,  Takahiro MARUYAMA

IPC: H01L21/764 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/02107 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/76224 ,  H01L21/764

Abstract: An object of the invention is to provide a semiconductor device having improved performance. A method of manufacturing a semiconductor device includes: forming a trench and then forming a first insulating film made of a silicon oxide film through CVD using a gas containing an O3 gas and a TEOS gas to cover the side surface of the trench with the insulating film; forming a second insulating film made of a silicon oxide film through PECVD to cover the side surface of the trench with the second insulating film via the first insulating film; and forming a third insulating film made of a silicon oxide film through CVD using a gas containing an O3 gas and a TEOS gas to close the trench with the third insulating film while leaving a space in the trench.

公开(公告)号：US20140175557A1

公开(公告)日：2014-06-26

申请号：US14191659

申请日：2014-02-27

Applicant: Renesas Electronics Corporation

Inventor： Tatsunori MURATA

IPC: H01L27/092 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L29/7833 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An n-channel MISFETQn is formed in an nMIS first formation region of a semiconductor substrate and a p-channel MISFETQp is formed in an adjacent pMIS second formation region of the semiconductor substrate. A silicon nitride film having a tensile stress is formed to cover the n-channel MISFETQn and the p-channel MISFETQp. In one embodiment, the silicon nitride film in the nMIS formation region and the pMIS formation region is irradiated with ultraviolet rays. Thereafter, a mask layer is formed to cover the silicon nitride film in the nMIS formation region and to expose the silicon nitride film in the pMIS formation region. The silicon nitride film in the pMIS formation region is then subjected to plasma processing, which relieves the tensile stress of the silicon nitride film in the pMIS formation region.

Abstract translation: n沟道MISFETQn形成在半导体衬底的nMIS第一形成区域中，并且p沟道MISFETQp形成在半导体衬底的相邻pMIS第二形成区域中。 形成具有拉伸应力的氮化硅膜以覆盖n沟道MISFETQn和p沟道MISFETQp。 在一个实施例中，用紫外线照射nMIS形成区域和pMIS形成区域中的氮化硅膜。 此后，形成掩模层以覆盖nMIS形成区域中的氮化硅膜并暴露pMIS形成区域中的氮化硅膜。 然后对pMIS形成区域中的氮化硅膜进行等离子体处理，这减轻了pMIS形成区域中的氮化硅膜的拉伸应力。