公开(公告)号：US20230145662A1

公开(公告)日：2023-05-11

申请号：US17965308

申请日：2022-10-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koichi TAKEDA ,  Takahiro SHIMOI ,  Masaya NAKANO ,  Hidenori MITANI ,  Yoshinobu KANEDA

IPC: H03F3/45

CPC classification number: H03F3/45744 ,  H03F3/45497 ,  H03F3/45511

Abstract: Speed enhancement of data reading is achieved while suppressing an influence of an offset voltage of a differential amplifier. The differential amplifier includes: a current source that is connected to a first power supply in which a suppliable current is a first current; an active element pair that is connected to the current source, and amplifies a signal input to an input terminal pair to output an output signal pair; a load element pair that is connected to a second power supply different in power supply voltage from the first power supply, the load element pair serving for outputting the output signal pair to an output terminal pair; and a capacitance element pair that is inserted between an external input terminal pair and the input terminal pair; a switching element pair that charges the capacitance element pair to generate a voltage, which is obtained by converting an offset voltage of the input terminal pair into an input voltage, in the capacitance element pair by short-circuiting corresponding terminals between the output terminal pair and the input terminal pair; and a current control circuit that controls a current suppliable by the current source to a second current larger than the first current at a time of performing the charge.