公开(公告)号：US20160094239A1

公开(公告)日：2016-03-31

申请号：US14848924

申请日：2015-09-09

Applicant: Renesas Electronics Corporation

Inventor： Masaki FUJIWARA ,  Yasuo MORIMOTO ,  Takashi MATSUMOTO

IPC: H03M1/12 ,  H03K5/13 ,  H03M1/46

CPC classification number: H03M1/125 ,  H03K5/133 ,  H03K2005/00065 ,  H03M1/12 ,  H03M1/38 ,  H03M1/46 ,  H03M1/462 ,  H03M1/468

Abstract: A semiconductor device capable of accurately controlling the cycle of an internal clock signal. This semiconductor device, by using signal that is output from a sequence register of an asynchronous successive approximation type ADC when N times of comparison are completed, detects whether or not the signal and its delay signal are output when the period transitions from a comparison period to a sampling period, and generates, on the basis of the detection result, a delay control signal for controlling the cycle of an internal clock signal by controlling the delay times of the delay circuits.

Abstract translation: 能够精确地控制内部时钟信号的周期的半导体器件。 当N次比较完成时，通过使用从异步逐次逼近型ADC的序列寄存器输出的信号，该半导体器件检测当该周期从比较期间转变到该时间段时是否输出信号及其延迟信号 并根据检测结果生成用于通过控制延迟电路的延迟时间来控制内部时钟信号的周期的延迟控制信号。

公开(公告)号：US20250007529A1

公开(公告)日：2025-01-02

申请号：US18753046

申请日：2024-06-25

Applicant: Renesas Electronics Corporation

Inventor： Tetsuo MATSUI ,  Atsushi TANGODA ,  Keisaku SENTO ,  Masaki FUJIWARA

IPC: H03M1/08

Abstract: A semiconductor device capable of operating accurately while suppressing the propagation of interference noise, a control method for the semiconductor device, and a control program are provided. The semiconductor device includes a first AD converter of a charge redistribution type sequential comparison type that includes a redundant comparison operation in a sequential comparison operation and outputs a first input signal of an analog differential using a reference voltage to a first output signal of digital, a first pin to which the reference voltage is supplied from the outside, a first variable impedance circuit provided on a signal line between the first AD converter and capable of changing impedance, and a first control circuit 10 that controls the impedance of the first variable impedance circuit according to the operating condition of the first AD converter.

公开(公告)号：US20150042500A1

公开(公告)日：2015-02-12

申请号：US14336073

申请日：2014-07-21

Applicant: Renesas Electronics Corporation

Inventor： Masaki FUJIWARA ,  Yasuo MORIMOTO ,  Takashi MATSUMOTO

IPC: H03K3/86 ,  H03M1/38

CPC classification number: H03M1/125 ,  H03K5/133 ,  H03K2005/00065 ,  H03M1/12 ,  H03M1/38 ,  H03M1/46 ,  H03M1/462 ,  H03M1/468

Abstract: To provide a semiconductor device capable of accurately controlling the cycle of an internal clock signal. This semiconductor device, by using signal that is output from a sequence register of an asynchronous successive approximation type ADC when N times of comparison are completed, detects whether or not the signal and its delay signal are output when the period transitions from a comparison period to a sampling period, and generates, on the basis of the detection result, a delay control signal for controlling the cycle of an internal clock signal by controlling the delay times of the delay circuits.

Abstract translation: 提供能够精确地控制内部时钟信号的周期的半导体器件。 当N次比较完成时，通过使用从异步逐次逼近型ADC的序列寄存器输出的信号，该半导体器件检测当该周期从比较期间转变到该时间段时是否输出信号及其延迟信号 并根据检测结果生成用于通过控制延迟电路的延迟时间来控制内部时钟信号的周期的延迟控制信号。

公开(公告)号：US20200166606A1

公开(公告)日：2020-05-28

申请号：US16585924

申请日：2019-09-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi OSHIMA ,  Tetsuo MATSUI ,  Mitsuya FUKAZAWA ,  Katsuki TATEYAMA ,  Masaki FUJIWARA

IPC: G01S7/35 ,  H03M3/00 ,  G01S13/34

Abstract: A MASH type sigma delta AD converter includes a modulator, an analog filter filtering an extraction signal obtained by extracting a probe signal and an quantization error generated in a quantizer within a sigma delta modulator, a low speed AD converter performing an AD conversion of an output signal of the analog filter, a first adaptive filter searching for a transfer function of the sigma delta modulator, a second adaptive filter searching for a transfer function from an output of the modulator to the low speed AD converter via the analog filter, and a noise cancellation circuit cancelling the probe signal and the quantization error included in an output signal of the quantizer using the search results by the first and second adaptive filters.