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公开(公告)号：US20210382512A1
公开(公告)日：2021-12-09
申请号：US17405380
申请日：2021-08-18
发明人： CHE-WEI CHANG , KAI-YIN LIU , LIANG-HUAN LEI , SHIH-HSIUNG HUANG
摘要： Disclosed is a voltage reference buffer circuit including a first, second, third, and fourth bias generators and a first, second, third, and fourth driving components. The first, second, third, and fourth bias generators generate bias voltages to control the first, second, third, and fourth driving components respectively. The first, second, third, and fourth driving components are coupled in sequence, wherein the first and second driving components are different types of transistors and jointly output a first reference voltage, the third and fourth driving components are different types of transistors and jointly output a second reference voltage, and the group of the first and second driving components is separated from the group of the third and fourth driving components by a resistance load.
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公开(公告)号：US20180136681A1
公开(公告)日：2018-05-17
申请号：US15800935
申请日：2017-11-01
发明人： CHE-WEI CHANG , KAI-YIN LIU , LIANG-HUAN LEI , SHIH-HSIUNG HUANG
摘要： The present invention discloses a voltage reference buffer circuit. An embodiment of the voltage reference buffer circuit includes: a first bias generator configured to generate a first bias voltage; a second bias generator configured to generate a second bias voltage different from the first bias voltage; a first driving component coupled to a high voltage terminal, the first bias generator and a reference voltage output terminal, and configured to control a reference voltage at the reference voltage output terminal according to the first bias voltage; and a second driving component coupled to the reference voltage output terminal, the second bias generator and a low voltage terminal, and configured to control a current between the reference voltage output terminal and the second driving component according to the second bias voltage.
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