公开(公告)号：US11372436B2

公开(公告)日：2022-06-28

申请号：US16600664

申请日：2019-10-14

Applicant: QUALCOMM Incorporated

Inventor： Shamim Ahmed

IPC: G05F1/575 ,  G05F1/563 ,  G05F1/59 ,  G05F1/46

Abstract: A simultaneous low quiescent current and high performance low dropout (LDO) voltage regulator is disclosed. In some implementations, the LDO voltage regulator includes a first and a second pass transistors configured to receive an input voltage (Vin). The LDO voltage regulator further includes an error amplifying module having a first output, a second output, a first input, and a second input. The error amplifying module can further include a first output stage configured to drive the gate of the first pass transistor during a high performance (HP) mode, and a second output stage configured to drive the gate of the second pass transistor during the HP mode and during a low power (LP) mode.

公开(公告)号：US11959962B2

公开(公告)日：2024-04-16

申请号：US17808357

申请日：2022-06-23

Applicant: QUALCOMM Incorporated

Inventor： Chengyue Yu ,  Hua Guan ,  Yingjie Chen ,  Fan Yang ,  Yufei Pan ,  Jize Jiang ,  Shamim Ahmed

IPC: G01R31/28

CPC classification number: G01R31/2896 ,  G01R31/2853 ,  G01R31/2891

Abstract: Apparatus and techniques for an integrated circuit (IC) package to automatically detect, through an input/out pin, external component parameters and parasitics. An example IC package generally includes a pin for coupling to a component external to the IC package, and at least one of a resistance detector, an inductance detector, or a capacitance detector coupled to the pin, and configured to detect at least one of a resistance, an inductance, or a capacitance, respectively, of a lumped parameter model for the component external to the IC package. The resistance detector, inductance detector, or capacitance detector may also be configured to detect parasitics associated with at least one of the component, the pin, or a connection between the component and the pin.

公开(公告)号：US11003201B1

公开(公告)日：2021-05-11

申请号：US16696409

申请日：2019-11-26

Applicant: QUALCOMM Incorporated

Inventor： Shamim Ahmed ,  David Eric Haglan

IPC: G05F1/575 ,  G05F1/59 ,  H04B1/3827

Abstract: A low-dropout (LDO) regulator and an associated method and apparatus are described. The LDO regulator generally includes a first transistor coupled between an input voltage node and an output voltage node of the LDO regulator. The LDO regulator further includes a first amplifier having an output coupled to a gate of the first transistor, wherein a feedback path couples the output voltage node to an input of the first amplifier. The LDO regulator further includes a second amplifier having an output coupled to an enable input of the first amplifier, wherein a voltage-sensing path couples the input voltage node to an input of the second amplifier. The LDO regulator further includes and a second transistor coupled between the gate of the first transistor and a reference potential node, the output of the second amplifier being coupled to a gate of the second transistor.