公开(公告)号：US09754655B2

公开(公告)日：2017-09-05

申请号：US15340266

申请日：2016-11-01

Applicant: QUALCOMM Incorporated

Inventor： Mosaddiq Saifuddin ,  SankaraRao Kunapareddy ,  Keunsoo Roh ,  Chun Xiang He ,  Pratik Patel ,  Nicholas Ambur ,  Jeremy Haugen

IPC: G11C16/06 ,  G11C11/406 ,  G11C7/10 ,  G11C11/408 ,  G06F13/16 ,  G06F1/32

CPC classification number: G11C11/40615 ,  G06F1/3225 ,  G06F1/3275 ,  G06F13/1636 ,  G11C7/1072 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4087

Abstract: In an embodiment, a dynamic random-access memory (DRAM) system configures an inactive portion of a DRAM die to operate in accordance with a self-refresh mode that is characterized by refreshes of the DRAM die being controlled by a local DRAM die controller integrated into the DRAM die. The DRAM system also configures an active portion of the DRAM die to operate in accordance with a controller-managed refresh mode while the inactive portion of the DRAM die operates in the self-refresh mode, the controller-managed refresh mode characterized by refreshes of the DRAM die being controlled by a controller that is external to the DRAM die.

公开(公告)号：US09824742B1

公开(公告)日：2017-11-21

申请号：US15249132

申请日：2016-08-26

Applicant: QUALCOMM Incorporated

Inventor： Mosaddiq Saifuddin ,  SankaraRao Kunapareddy

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G06F13/1636 ,  G11C11/40603 ,  G11C11/40622 ,  G11C11/4085

Abstract: Systems and method are directed to accessing a Dynamic Random Access Memory (DRAM) system. A DRAM controller is designed to determine that a DRAM bank of a DRAM system is in a self-refresh state and allow one or more commands to access the DRAM bank without exiting the self-refresh state. The DRAM controller may select these one or more commands, based on one or more of a clock frequency, traffic conditions related to requests for accessing the DRAM bank, or a command type. The one or more commands may include at least one of read (RD), write (WR), or precharge (PRE) commands received while the DRAM bank is in the self-refresh state.

公开(公告)号：US20170316818A1

公开(公告)日：2017-11-02

申请号：US15249132

申请日：2016-08-26

Applicant: QUALCOMM Incorporated

Inventor： Mosaddiq Saifuddin ,  SankaraRao Kunapareddy

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G06F13/1636 ,  G11C11/40603 ,  G11C11/40622 ,  G11C11/4085

Abstract: Systems and method are directed to accessing a Dynamic Random Access Memory (DRAM) system. A DRAM controller is designed to determine that a DRAM bank of a DRAM system is in a self-refresh state and allow one or more commands to access the DRAM bank without exiting the self-refresh state. The DRAM controller may select these one or more commands, based on one or more of a clock frequency, traffic conditions related to requests for accessing the DRAM bank, or a command type. The one or more commands may include at least one of read (RD), write (WR), or precharge (PRE) commands received while the DRAM bank is in the self-refresh state.