公开(公告)号：US20220311460A1

公开(公告)日：2022-09-29

申请号：US17211769

申请日：2021-03-24

Applicant: QUALCOMM Incorporated

Inventor： Meysam AZIN ,  Li LU ,  Anees HABIB ,  Chinmaya MISHRA ,  Damin CAO ,  Arul BALASUBRAMANIYAN ,  David Ta-hsiang LIN ,  Shuang ZHU ,  Dinesh Jagannath ALLADI

IPC: H04B1/04 ,  H03M1/46 ,  H03M3/00

Abstract: Aspects of the disclosure relate to an apparatus for wireless communication. The apparatus may include a set of power detectors configured to generate a set of analog signals related to a set of output signal power levels of a set of transmit chains of a transmitter, respectively; an analog summer; a set of switching devices configured to send a selected one or more of the set of analog signals to the analog summer, and substantially isolated unselected one or more of the set of power detectors from the analog summer, wherein the analog summer is configured to generate a cumulative analog signal based on a sum of the selected one or more of the set of analog signals; an analog-to-digital converter (ADC) configured to generate a digital signal based on the cumulative analog signal; and a controller configured to control the set of switching devices.

公开(公告)号：US20180352321A1

公开(公告)日：2018-12-06

申请号：US15613871

申请日：2017-06-05

Applicant: QUALCOMM Incorporated

Inventor： Jingxue LU ,  Vijayakumar DHANASEKARAN ,  Meysam AZIN ,  Arash MASHAYEKHI ,  Kshitij YADAV

IPC: H04R1/10 ,  H03F3/183 ,  H04R1/06

CPC classification number: H04R1/1091 ,  H03F1/26 ,  H03F3/183 ,  H03F3/187 ,  H03F3/2173 ,  H03F3/45475 ,  H03F3/68 ,  H03F2200/03 ,  H04R1/06

Abstract: An example apparatus includes an output jack including a ground pole and a power output pole, a power supply circuit configured to generate a power signal, a coupler circuit operably coupled to the ground pole and the power output pole of the output jack, such that the coupler circuit is configured to couple the power signal with a noise signal on the ground pole to generate a combined output signal on the power output pole.

公开(公告)号：US20150280660A1

公开(公告)日：2015-10-01

申请号：US14230909

申请日：2014-03-31

Applicant: QUALCOMM Incorporated

Inventor： Meysam AZIN ,  Arash MEHRABI ,  Wenchang HUANG

IPC: H03F3/185 ,  H03F3/00 ,  H04R3/00 ,  H03F3/45

CPC classification number: H03F3/185 ,  H03F3/005 ,  H03F3/181 ,  H03F3/187 ,  H03F3/45179 ,  H03F3/45183 ,  H03F2200/03 ,  H03F2203/45016 ,  H03F2203/45514 ,  H03H19/004 ,  H04R3/00

Abstract: An integrated DC blocking amplifier circuit, including: an operational amplifier configured in a differential amplifier; and at least first and second two-stage switched-capacitor circuits, each two stage switched-capacitor circuit including a first-stage circuit and a second-stage circuit, wherein the first two-stage switched capacitor circuit is connected to a positive feedback path of the operational amplifier and the second two-stage switched capacitor circuit is connected to a negative feedback path of the operational amplifier, wherein the first-stage circuit is switched at a relatively low switching frequency, while the second-stage circuit is switched at a relatively high switching frequency.

Abstract translation: 一种集成的DC阻塞放大器电路，包括：配置在差分放大器中的运算放大器; 以及至少第一和第二两级开关电容器电路，每个两级开关电容器电路包括第一级电路和第二级电路，其中所述第一两级开关电容器电路连接到正反馈路径 运算放大器和第二两级开关电容器电路连接到运算放大器的负反馈路径，其中第一级电路以相对低的开关频率切换，而第二级电路以 开关频率相对较高。