公开(公告)号：US20180053740A1

公开(公告)日：2018-02-22

申请号：US15243923

申请日：2016-08-22

Applicant: QUALCOMM Incorporated

Inventor： Manoj KAKADE ,  Haiyong XU ,  Ruey Kae ZANG ,  Yue LI ,  Xiaonan ZHANG ,  Christine HAU-RIEGE

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2924/07025 ,  H01L2924/1206 ,  H01L2924/15313 ,  H05K1/111 ,  H05K1/185 ,  H05K2201/09472

Abstract: The present disclosure provides packages and methods for fabricating packages. A package may comprise a wafer-level package (WLP) layer comprising first and second WLP contacts and first and second conductive pillars disposed on the first and second WLP contacts. Each conductive pillar may comprise a surface opposite the WLP contact that forms an array pad. The array pads may have different sizes. The package may further comprise a mold over the WLP layer and at least partially surrounding the conductive pillars, wherein the mold compound and the first array pads form a substantially planar LGA contact surface that is configured to couple the package to a land grid array.