公开(公告)号：US20130270718A1

公开(公告)日：2013-10-17

申请号：US13919230

申请日：2013-06-17

Applicant: QUALCOMM Incorporated

Inventor： Fifin Sweeney ,  Jason R. Gonzalez

IPC: H01L25/00

CPC classification number: H01L25/00 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/25 ,  H01L25/0657 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/00

Abstract: A package includes a printed circuit board (PCB) having a first side and a second side and a thickness between the first side and the second side and a stacked die including a top die mounted on a bottom die, the bottom die being at least partially embedded in the PCB. Also a method of forming a package that includes forming an opening in a top surface of the PCB layer, placing a stacked die including a top die stacked on a bottom die into the opening, laminating the PCB layer to form a laminate layer, and forming an electrical connection with the stacked die.

Abstract translation: 封装包括具有第一侧和第二侧以及第一侧和第二侧之间的厚度的印刷电路板（PCB），以及包括安装在底模上的顶模的堆叠模，所述底模至少部分地 嵌入在PCB中。 还有一种形成封装的方法，包括在PCB层的上表面形成开口，将包括堆叠在底模上的顶模的堆叠裸片放入开口中，层压PCB层以形成层压层，并形成 与堆叠的模具电连接。