公开(公告)号：US11962440B2

公开(公告)日：2024-04-16

申请号：US17550993

申请日：2021-12-14

Applicant: QUALCOMM Incorporated

Inventor： Darius Valaee ,  Patrick Isakanian

IPC: H04L25/03 ,  G11C7/06

CPC classification number: H04L25/03267 ,  G11C7/065 ,  H04L25/03057

Abstract: In certain aspects, a comparator includes an input stage and a regeneration stage. The input stage includes a first input circuit coupled to a first node and a second node, a first switching transistor configured to enable the first input circuit if a previous bit value is one, a second input circuit coupled to the first node and the second node, and a second switching transistor configured to enable the second input circuit if the previous bit value is zero. The regeneration stage includes a first inverter, a second inverter cross coupled with the first inverter, a first drive transistor coupled to the first inverter, wherein a gate of the first drive transistor is coupled to the second node, and a second drive transistor coupled to the second inverter, wherein a gate of the second drive transistor is coupled to the first node.

公开(公告)号：US11824695B2

公开(公告)日：2023-11-21

申请号：US17579405

申请日：2022-01-19

Applicant: QUALCOMM Incorporated

Inventor： Darius Valaee ,  Patrick Isakanian ,  Srivatsan Thiruvengadam

IPC: H04L27/01 ,  H04L25/06 ,  H04L25/03

CPC classification number: H04L27/01 ,  H04L25/03343 ,  H04L25/069

Abstract: An equalizing transmitter coupled to a serial transmission line has a driver circuit coupled between an input signal and the serial transmission line, the driver circuit being configured to receive power at a first voltage level. The equalizing transmitter has one or more helper circuits, each helper circuit being configured to receive a control signal and to pull the serial transmission line to a second voltage level when a pulse is present in the control signal. The second voltage level may be greater than the first voltage level. The equalizing transmitter has one or more pulse generation circuits, each pulse generation circuit being configured to receive the input signal and a delayed version of the input signal and to provide the pulse in the control signal when a difference in voltage state is detected between the input signal and the delayed version of the input signal.

公开(公告)号：US12021669B2

公开(公告)日：2024-06-25

申请号：US17985498

申请日：2022-11-11

Applicant: QUALCOMM Incorporated

Inventor： Patrick Isakanian ,  Darius Valaee

IPC: H04L25/03

CPC classification number: H04L25/03057

Abstract: An input stage of a comparator includes a first transistor, wherein a gate of the first transistor is coupled to a first input of the input stage, a second transistor, wherein a gate of the second transistor is coupled to a second input of the input stage, a third transistor coupled in series with the first transistor, and a fourth transistor coupled in series with the second transistor. The input stage also includes a fifth transistor, wherein a gate of the fifth transistor is configured to receive a first decision feedback signal, and a drain of the fifth transistor is coupled to a gate of the third transistor. The input stage further includes a sixth transistor, wherein a gate of the sixth transistor is configured to receive a second decision feedback signal, and a drain of the sixth transistor is coupled to a gate of the fourth transistor.