公开(公告)号：US20170353186A1

公开(公告)日：2017-12-07

申请号：US15171487

申请日：2016-06-02

Applicant: QUALCOMM Incorporated

Inventor： Qi YE ,  Animesh DATTA ,  Bo PANG

IPC: H03K19/00 ,  H03K19/21 ,  H03K3/037

CPC classification number: H03K19/0016 ,  H03K3/012 ,  H03K3/037 ,  H03K19/21

Abstract: A low clock power data-gated flip-flop is provided. The data-gated flip-flop includes an exclusive OR component including a first exclusive OR input, a second exclusive OR input, and a first exclusive OR output. The first exclusive OR input is configured to receive a data input to the data-gated flip-flop. The data-gated flip-flop includes a first latch including a first latch data input and a first latch reset input, the first exclusive OR output being coupled to the first latch data input and the first latch reset input. The data-gated flip-flop includes a second latch having a data output, the data output coupled to the second exclusive OR input.

公开(公告)号：US20240313939A1

公开(公告)日：2024-09-19

申请号：US18184341

申请日：2023-03-15

Applicant: QUALCOMM Incorporated

Inventor： Bo PANG ,  Andrew WEIL ,  Matthew Chauncey KUSBIT ,  Mahmoud ELHEBEARY ,  Benjamin GRIFFITTS ,  Xiaohong QUAN

IPC: H04L7/00

CPC classification number: H04L7/0016

Abstract: An apparatus, including: a switched capacitor configured to generate a switched capacitor voltage based on an input clock signal and a current; a current digital-to-analog converter (DAC) configured to generate the current based on a first digital signal; a first reference voltage generator configured to generate a first reference voltage; and a first voltage comparing device configured to generate a first frequency deviation detection signal based on a comparison of the switched capacitor voltage to the first reference voltage.