公开(公告)号：US20190012271A1

公开(公告)日：2019-01-10

申请号：US15641765

申请日：2017-07-05

Applicant: QUALCOMM Incorporated

Inventor： Christophe AVOINNE ,  Samar ASBE ,  Thomas ZENG ,  Jean-Louis TARDIEUX ,  Jeffrey SHABEL ,  Azzedine TOUZNI

IPC: G06F12/14 ,  G06F12/1027 ,  G06F12/1009 ,  G06F1/32

Abstract: One feature pertains to an apparatus that includes a memory circuit, a system memory-management unit (SMMU), and a processing circuit. The memory circuit stores an executable program associated with a client. The SMMU enforces memory access control policies for the memory circuit, and includes a plurality of micro-translation lookaside buffers (micro-TLBs), macro-TLB, and a page walker circuit. The plurality of micro-TLBs include a first micro-TLB that enforces memory access control policies for the client. The processing circuit loads memory address translations associated with the executable program into the first micro-TLB, and initiates isolation mode for the first micro-TLB causing communications between the first micro-TLB and the macro-TLB and between the first micro-TLB and the page walker circuit to be severed. The first micro-TLB continues to enforce memory access control policies for the client while in isolation mode.

公开(公告)号：US20180253314A1

公开(公告)日：2018-09-06

申请号：US15448232

申请日：2017-03-02

Applicant: QUALCOMM Incorporated

Inventor： Dhamim PACKER ALI ,  Yanru LI ,  Ashutosh SHRIVASTAVA ,  Azzedine TOUZNI ,  Mamta DESAI

IPC: G06F9/44

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of operating a system-on-chip (SoC). The method includes selecting a CPU core of a plurality of CPU cores of the SoC to boot the SoC based on information indicative of the quality of the plurality of CPU cores stored on the SoC. The method includes running boot code on the selected CPU.