Programmable bit alignment at serial-to-parallel stage of SerDes

    公开(公告)号:US10536165B1

    公开(公告)日:2020-01-14

    申请号:US16280985

    申请日:2019-02-20

    Inventor: Anand Gaurav Bo Sun

    Abstract: In certain aspects, a serial-to-parallel converter includes multiple cascaded stages configured to convert a serial data stream into multiple parallel data signals, wherein each of the stages includes one or more demultiplexers. The serial-to-parallel converter also includes demultiplexer control circuits, wherein each of the demultiplexer control circuits is coupled to the one or more demultiplexers of a respective one of the stages, and a pattern detector coupled to the demultiplexer control circuits.

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