公开(公告)号：US12174757B1

公开(公告)日：2024-12-24

申请号：US18338653

申请日：2023-06-21

Applicant: QUALCOMM INCORPORATED

Inventor： Santhosh Reddy Akavaram ,  Prakhar Srivastava ,  Sridhar Anumala ,  Ramacharan Sundararaman ,  Sonali Jabreva ,  Khushboo Kumari ,  Sanjay Verdu

IPC: G06F13/16

Abstract: Methods and apparatuses are provided to reduce latencies associated with state transitions in die-to-die interconnect architectures. In one example, a physical layer of a die detects a first event indicating a transition to a lower power state. In response to the first event, the physical layer transitions to a lower power state where one or more clock configuration values are read from registers and stored in memory. The physical layer then detects a second event indicating a transition to an active state. In response to the second event, the physical layer reads the clock configuration values from the memory, and writes the clock configuration values to the registers. The physical layer then transitions to a power stabilization state, and remains in the power stabilization state for an amount of time to allow clocks to stabilize. The physical layer then transitions to a training state.

公开(公告)号：US20240370378A1

公开(公告)日：2024-11-07

申请号：US18310295

申请日：2023-05-01

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy Akavaram ,  Sonali Jabreva ,  Prakhar Srivastava

IPC: G06F12/1009

Abstract: This disclosure provides systems, methods, and devices for memory systems that support updating a logical to physical (L2P) table of a host device in accordance with one or more updates to a corresponding L2P table of a memory system. In a first aspect, a method of accessing data in a flash memory system includes a host memory controller receiving an indication of an update to a first logical to physical (L2P) table stored on a first memory of a memory system and updating a second L2P table stored on a second memory of the host device in accordance with the update to the first L2P table. Other aspects and features are also claimed and described.

公开(公告)号：US12056364B1

公开(公告)日：2024-08-06

申请号：US18296319

申请日：2023-04-05

Applicant: QUALCOMM Incorporated

Inventor： Yogananda Rao Chillariga ,  Santhosh Reddy Akavaram ,  Prakhar Srivastava ,  Sonali Jabreva ,  Chintalapati Bharath Sai Varma

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0656 ,  G06F3/0679

Abstract: Aspects of the present disclosure provide various techniques, apparatuses, and methods that can improve the memory resource utilization of a data storage device that uses nonvolatile memory (NVM) to store data. In some aspects, the data storage device can be provided with multiple write buffers to improve the write throughput of the device. In some aspects, the data storage device can use a utilization array to keep track of the utilization information of each write buffer. In some aspects, the data storage device can repurpose the memory of a write buffer with low utilization to serve an active logical unit which becomes full, thus preserving the function of the write buffer of the active logical unit.

公开(公告)号：US12197775B2

公开(公告)日：2025-01-14

申请号：US18189141

申请日：2023-03-23

Applicant: QUALCOMM Incorporated

Inventor： Santhosh Reddy Akavaram ,  Sonali Jabreva ,  Prakhar Srivastava ,  Surendra Paravada ,  Yogananda Rao Chillariga ,  Madhu Yashwanth Boenapalli

IPC: G06F3/06

Abstract: Aspects of the present disclosure provide various techniques, apparatuses, and methods that can improve the write throughout of a data storage device. In some aspects, the storage device can be provided with multiple write buffers to improve write throughput. In some aspects, the data storage device can continue to handle commands using a command queue while performing a write buffer flush operation. Therefore, the data storage device can avoid suspending the write buffer flush operation when a new command is received by the command queue. In some aspects, the storage device can perform a write buffer flush operation when a command queue is not empty.