公开(公告)号：US11169593B2

公开(公告)日：2021-11-09

申请号：US15929732

申请日：2020-05-19

Applicant: QUALCOMM Incorporated

Inventor： Raghavendra Srinivas ,  Bharat Kumar Rangarajan ,  Rajesh Arimilli

IPC: G06F1/00 ,  G06F1/3296 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/324 ,  G11C5/14 ,  G06F1/3206 ,  G06F1/26

Abstract: Various aspects are described herein. In some aspects, the disclosure provides selective coupling of portions of a memory structure to voltage supplies. Certain aspects provide a computing device. The computing device includes a memory comprising a plurality of portions that are individually power collapsible. The computing device further includes a first voltage rail supplying a first voltage. The computing device further includes a second voltage rail supplying a second voltage. The computing device further includes a plurality of switching circuits, each switching circuit configured to selectively couple a corresponding one of the plurality of portions with the first voltage rail or the second voltage rail. The computing device further includes a controller configured to control each of the plurality of switching circuits based on a current active mode of the memory, and a current operating mode of each of the plurality of portions.

公开(公告)号：US20190324932A1

公开(公告)日：2019-10-24

申请号：US15958438

申请日：2018-04-20

Applicant: QUALCOMM Incorporated

Inventor： Raghavendra Srinivas ,  Kaustav Roychowdhury ,  Siddesh Halavarthi Math Revana

IPC: G06F13/24 ,  G06F9/48 ,  G06F9/38 ,  G06F9/54 ,  G06F12/084 ,  G06F11/34 ,  G06F11/30

Abstract: Providing interrupt service routine (ISR) prefetching in multicore processor-based systems is disclosed. In one aspect, a multicore processor-based system provides an ISR prefetch control circuit communicatively coupled to an interrupt controller and a plurality of instruction fetch units (IFUs) of a corresponding plurality of processor elements (PEs). Upon receiving an interrupt directed to a target PE of the plurality of PEs, the interrupt controller provides an interrupt request (IRQ) identifier to the ISR prefetch control circuit. Based on the IRQ identifier, the ISR prefetch control circuit fetches an ISR pointer to an ISR corresponding to the IRQ identifier. The ISR prefetch control circuit next selects a prefetch PE of the plurality of PEs to perform a prefetch operation to retrieve the ISR on behalf of the target PE, and provides an ISR prefetch request, including the ISR pointer, to an IFU of the prefetch PE.

公开(公告)号：US20200285584A1

公开(公告)日：2020-09-10

申请号：US16292178

申请日：2019-03-04

Applicant: QUALCOMM INCORPORATED

Inventor： Raghavendra Srinivas ,  Kaustav Roychowdhury ,  Siddesh Halavarthi Math Revana ,  Srivatsa Vaddagiri ,  Satyaki Mukherjee

IPC: G06F12/0891 ,  G06F12/0837 ,  G06F12/0842 ,  G06F12/0897

Abstract: Aborting a cache memory flush may include initiating a flush operation in which a plurality of cache lines are flushed from a cache memory associated with a processor core that is entering a power collapse mode. Assertion of a wake-up signal associated with the processor core entering the power collapse mode may be detected. The wake-up signal may occur before completion of the flush operation. The flush operation may cease or abort in response to detecting the wake-up signal.

公开(公告)号：US10732697B2

公开(公告)日：2020-08-04

申请号：US15978902

申请日：2018-05-14

Applicant: QUALCOMM Incorporated

Inventor： Raghavendra Srinivas ,  Abhijit Joshi ,  Bharat Kavala ,  Abinash Roy

IPC: G06F1/3234 ,  G06F1/3287 ,  G06F1/30 ,  G06F1/26 ,  G06F1/28 ,  G06F1/18

Abstract: Various aspects are described herein. In some aspects, the disclosure provides techniques for reducing latency in switching computing cores of a computing system between operating modes. Certain aspects provide a computing device including a plurality of computing cores, each configured to operate in any one of a plurality of operating modes. The computing device further includes a first voltage rail and a plurality of components, each associated with one of the computing cores. The computing device further includes a plurality of switches, each switch configured to selectively couple a corresponding one of the plurality of components to the first voltage rail. The computing device further includes a controller configured to determine a current operating mode of each of the plurality of computing cores and switch the plurality of switches at a first selected switching rate based on the determined current operating mode of each of the plurality of computing cores.

公开(公告)号：US10691195B2

公开(公告)日：2020-06-23

申请号：US15908534

申请日：2018-02-28

Applicant: QUALCOMM Incorporated

Inventor： Raghavendra Srinivas ,  Bharat Kumar Rangarajan ,  Rajesh Arimilli

IPC: G06F1/00 ,  G06F1/3296 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/324 ,  G11C5/14 ,  G06F1/3206 ,  G06F1/26

Abstract: Various aspects are described herein. In some aspects, the disclosure provides selective coupling of portions of a memory structure to voltage supplies. Certain aspects provide a computing device. The computing device includes a memory comprising a plurality of portions that are individually power collapsible. The computing device further includes a first voltage rail supplying a first voltage. The computing device further includes a second voltage rail supplying a second voltage. The computing device further includes a plurality of switching circuits, each switching circuit configured to selectively couple a corresponding one of the plurality of portions with the first voltage rail or the second voltage rail. The computing device further includes a controller configured to control each of the plurality of switching circuits based on a current active mode of the memory, and a current operating mode of each of the plurality of portions.

公开(公告)号：US10459510B1

公开(公告)日：2019-10-29

申请号：US16250953

申请日：2019-01-17

Applicant: QUALCOMM Incorporated

Inventor： Raghavendra Srinivas ,  Uday Shankar Mudigonda ,  Giby Samson ,  Ramaprasath Vilangudipitchai ,  Dorav Kumar

IPC: H03K19/00 ,  H03K17/28 ,  G06F1/32 ,  G06F1/3234 ,  H03K17/693 ,  H03K17/284

Abstract: In certain aspects, an apparatus includes a first plurality of power switch devices. Each of the first plurality of power switch devices includes a delay line having a programmable time delay, and a power switch coupled between a supply rail and a circuit block, wherein the power switch has a control input coupled to the delay line. The apparatus also includes a switch manager configured to program the time delays of the delay lines in the first plurality of power switch devices based on a number of active circuit blocks in a system.