公开(公告)号：US20140223093A1

公开(公告)日：2014-08-07

申请号：US13798767

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： David Paul Hoff ,  Tracey A. Della Rova ,  Jason P. Martzloff

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G06F7/74 ,  G11C15/043 ,  H03K19/0013

Abstract: The hybrid dynamic-static encoder described herein may combine dynamic and static structural and logical design features that strategically partition dynamic nets and logic to substantially eliminate redundancy and thereby provide area, power, and leakage savings relative to a fully dynamic encoder with an equivalent logic delay. For example, the hybrid dynamic-static encoder may include identical top and bottom halves, which may be combined to produce final encoded index, hit, and multi-hit outputs. Each encoder half may use a dynamic net for each index bit with rows that match a search key dotted. If a row has been dotted to indicate that the row matches the search key, the dynamic nets associated therewith may be evaluated to reflect the index associated with the row. Accordingly, the hybrid dynamic-static encoder may have a reduced set of smaller dynamic nets that leverage redundant pull-down structures across the index, hit, and multi-hit dynamic nets.

Abstract translation: 本文描述的混合动态静态编码器可以组合动态和静态结构和逻辑设计特征，其策略性地分割动态网络和逻辑以基本上消除冗余，从而相对于具有等效逻辑延迟的全动态编码器提供面积，功率和泄漏节省 。 例如，混合动态静态编码器可以包括相同的顶部和底部两半，其可以被组合以产生最终编码索引，命中和多命中输出。 每个编码器一半可以为每个索引位使用动态网络，其中匹配搜索关键点的行。 如果已经点划线以指示该行与搜索关键字匹配，则可以评估与之相关联的动态网络以反映与该行相关联的索引。 因此，混合动态静态编码器可以具有减小的较小动态网络集合，其利用索引，命中和多命中动态网络上的冗余下拉结构。

公开(公告)号：US09165650B2

公开(公告)日：2015-10-20

申请号：US13798767

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： David Paul Hoff ,  Tracey A. Della Rova ,  Jason P. Martzloff

IPC: G11C15/04 ,  G06F7/74

CPC classification number: G11C15/04 ,  G06F7/74 ,  G11C15/043 ,  H03K19/0013

Abstract: The hybrid dynamic-static encoder described herein may combine dynamic and static structural and logical design features that strategically partition dynamic nets and logic to substantially eliminate redundancy and thereby provide area, power, and leakage savings relative to a fully dynamic encoder with an equivalent logic delay. For example, the hybrid dynamic-static encoder may include identical top and bottom halves, which may be combined to produce final encoded index, hit, and multi-hit outputs. Each encoder half may use a dynamic net for each index bit with rows that match a search key dotted. If a row has been dotted to indicate that the row matches the search key, the dynamic nets associated therewith may be evaluated to reflect the index associated with the row. Accordingly, the hybrid dynamic-static encoder may have a reduced set of smaller dynamic nets that leverage redundant pull-down structures across the index, hit, and multi-hit dynamic nets.

Abstract translation: 本文描述的混合动态静态编码器可以组合动态和静态结构和逻辑设计特征，其策略性地分割动态网络和逻辑以基本上消除冗余，从而相对于具有等效逻辑延迟的全动态编码器提供面积，功率和泄漏节省 。 例如，混合动态静态编码器可以包括相同的顶部和底部两半，其可以被组合以产生最终编码索引，命中和多命中输出。 每个编码器一半可以为每个索引位使用动态网络，其中匹配搜索关键点的行。 如果已经点划线以指示该行与搜索关键字匹配，则可以评估与之相关联的动态网络以反映与该行相关联的索引。 因此，混合动态静态编码器可以具有减小的较小动态网络集合，其利用索引，命中和多命中动态网络上的冗余下拉结构。