公开(公告)号：US20230401152A1

公开(公告)日：2023-12-14

申请号：US17827302

申请日：2022-05-27

Applicant: QUALCOMM Incorporated

Inventor： Hithesh Hassan LEPAKSHA ,  Sharath Kumar NAGILLA ,  Darshan Kumar NANDANWAR ,  Nirav Narendra DESAI ,  Venkata Biswanath DEVARASETTY

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/468

Abstract: Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting a number of cache lines that satisfy an eviction criteria based on a deterministic cache eviction policy in each cache way of a group of cache ways; selecting at least one cache way from the group for collapse, based on its corresponding number of cache lines that satisfy the eviction criteria; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.

公开(公告)号：US20240281250A1

公开(公告)日：2024-08-22

申请号：US18171012

申请日：2023-02-17

Applicant: QUALCOMM INCORPORATED

Inventor： Darshan Kumar NANDANWAR

IPC: G06F9/30

CPC classification number: G06F9/30043

Abstract: A system for performing energy-efficient computing reduces the amount of data that is transferred between a processor and an external memory device. The processor and the external memory device are equipped with first and second near data processing control units (NCUs), respectively, that coordinate offloading of preselected subprocesses from the processor to a first processing circuit disposed on or near the external memory device. When the processor is performing one of these preselected processes, the first NCU transmits commands and memory addresses to the second NCU. The processing circuit on or near the memory device performs the subprocess or subprocesses and the result is forwarded by the second NCU to the first NCU, which forwards it to the processor to complete the process.

公开(公告)号：US20240361931A1

公开(公告)日：2024-10-31

申请号：US18307686

申请日：2023-04-26

Applicant: QUALCOMM INCORPORATED

Inventor： Hithesh Hassan LEPAKSHA ,  Darshan Kumar NANDANWAR ,  Sharath Kumar NAGILLA

IPC: G06F3/06

CPC classification number: G06F3/0635 ,  G06F3/0604 ,  G06F3/0685

Abstract: Systems and methods for reducing data movement when performing large-sized memory transactions in a memory hierarchy are provided. For certain preselected types of large-size memory transactions, such as memset and memcopy operations, for example, logic of the processor determines whether the type of memory transaction being queued is one of the preselected types for which alteration of the path of data movement is an option. Logic of the processor also determines whether the size of the memory block associated with the transaction is sufficiently large to warrant altering the path of data movement. If the type is one of the preselected types and the size of the memory block is sufficiently large, logic of the LLC controller selects an altered path for data movement that reduces data movement and performs the transaction using the altered path.

公开(公告)号：US20250103545A1

公开(公告)日：2025-03-27

申请号：US18473119

申请日：2023-09-22

Applicant: QUALCOMM Incorporated

Inventor： Hithesh Hassan LEPAKSHA ,  Sharath Kumar NAGILLA ,  Darshan Kumar NANDANWAR

IPC: G06F15/78

Abstract: A method of execution unit (EU) sharing between processor cores is described. The method includes encountering a structural hazard associated with an issued instruction in an instruction queue of a dispatch stage inside an active processor core. The method also includes issuing a request for an idle execution unit of an inactive processor core. The method further includes sending a transaction containing source operands of the issued instruction, and a word address of a result buffer as a destination operand to an allocated EU of the inactive processor core. The method also includes replacing the issued instruction in the instruction queue with a load operation to forward a result of the issued instruction from the result buffer based on the word address.

公开(公告)号：US20240272698A1

公开(公告)日：2024-08-15

申请号：US18168071

申请日：2023-02-13

Applicant: QUALCOMM INCORPORATED

Inventor： Darshan Kumar NANDANWAR

IPC: G06F1/324 ,  G06F1/3206 ,  G06F1/3296 ,  G06F11/30

CPC classification number: G06F1/324 ,  G06F1/3206 ,  G06F1/3296 ,  G06F11/3058

Abstract: A system for performing thermal mitigation in a multi-core processor determines which processing core(s) of the processor is responsible for causing the temperature to rise to an undesired level and then performs one or more thermal mitigation steps only in the responsible core to avoid degrading performance of the other cores. The system monitors digital activity (DA) of the pipeline stages of the cores, determines when the DA of a processing stage has caused temperature to rise to a particular level and then reduces the DA of at least one processing stage of the responsible core in order to reduce temperature. The system can also take one or more other thermal mitigation steps based on monitored temperature values, such as reducing clock frequency or selecting a different V/F corner of the responsible core.

公开(公告)号：US20240402772A1

公开(公告)日：2024-12-05

申请号：US18329394

申请日：2023-06-05

Applicant: QUALCOMM INCORPORATED

Inventor： Darshan Kumar NANDANWAR ,  Kartik Gunvantbhai DESAI ,  Raghava Rao MV

IPC: G06F1/20 ,  G06F1/28

Abstract: A system for performing predictive run-time thermal mitigation in a processor uses at least a first temperature sensor and a first power sensor or meter to measure a junction temperature, TJUNC, value and power consumption, PTOTAL, value in the processor and predicts what a temperature, TEMPPRED, value of the processor will be in a later clock cycle of the processor based at least in part on the TJUNC and PTOTAL values. If the TEMPPRED value exceeds a preselected temperature threshold, THTEMP, value, one or more thermal mitigation actions are taken to ensure that a future TJUNC value measured n sample periods from the current sample period k of the processor will not exceed the THTEMP value.

公开(公告)号：US20230401156A1

公开(公告)日：2023-12-14

申请号：US17806291

申请日：2022-06-10

Applicant: QUALCOMM Incorporated

Inventor： Hithesh Hassan LEPAKSHA ,  Sharath Kumar NAGILLA ,  Darshan Kumar NANDANWAR ,  Nirav Narendra DESAI ,  Venkata Biswanath DEVARASETTY

IPC: G06F12/0891 ,  G06F12/0895 ,  G06F12/123

CPC classification number: G06F12/0891 ,  G06F12/0895 ,  G06F12/124

Abstract: Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting, in each cache way of a group of cache ways, a number of dirty cache lines having dirty bits indicating the cache line has been modified; selecting, from the group, at least one cache way for collapse, based on its corresponding number of dirty cache lines; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.