公开(公告)号：US08341433B2

公开(公告)日：2012-12-25

申请号：US11969268

申请日：2008-01-04

Applicant: Paul Artman ,  Stuart Berke

Inventor： Paul Artman ,  Stuart Berke

IPC: G06F1/00 ,  G05D23/00 ,  H05K7/20 ,  F24F7/00

CPC classification number: G06F1/26 ,  G06F1/206 ,  Y02D10/16

Abstract: A method for managing the power consumption of an information handling system including a processor and an associated cooling system. The method may include providing power to the cooling system based on a performance/power balance setting, accepting a user input to adjust the performance/power balance setting, and adjusting the power provided to the cooling system based on the adjusted performance/power balance setting. The performance/power balance setting may define a balance between performance of the processor and power consumption of the associated cooling system.

Abstract translation: 一种用于管理包括处理器和相关冷却系统的信息处理系统的功耗的方法。 该方法可以包括基于性能/功率平衡设置向冷却系统提供电力，接受用户输入以调整性能/功率平衡设置，以及基于经调整的性能/功率平衡设置来调整提供给冷却系统的功率 。 性能/功率平衡设置可以定义处理器的性能和相关冷却系统的功耗之间的平衡。

公开(公告)号：US20090177334A1

公开(公告)日：2009-07-09

申请号：US11969268

申请日：2008-01-04

Applicant: Paul Artman ,  Stuart Berke

Inventor： Paul Artman ,  Stuart Berke

IPC: G01K15/00 ,  G06F1/00

CPC classification number: G06F1/26 ,  G06F1/206 ,  Y02D10/16

Abstract: A method for managing the power consumption of an information handling system including a processor and an associated cooling system. The method may include providing power to the cooling system based on a performance/power balance setting, accepting a user input to adjust the performance/power balance setting, and adjusting the power provided to the cooling system based on the adjusted performance/power balance setting. The performance/power balance setting may define a balance between performance of the processor and power consumption of the associated cooling system.

Abstract translation: 一种用于管理包括处理器和相关冷却系统的信息处理系统的功耗的方法。 该方法可以包括基于性能/功率平衡设置向冷却系统提供电力，接受用户输入以调整性能/功率平衡设置，以及基于经调整的性能/功率平衡设置来调整提供给冷却系统的功率 。 性能/功率平衡设置可以定义处理器的性能和相关冷却系统的功耗之间的平衡。

公开(公告)号：US20070226456A1

公开(公告)日：2007-09-27

申请号：US11386026

申请日：2006-03-21

Applicant: Mark Shaw ,  Stuart Berke ,  Denis Foley

Inventor： Mark Shaw ,  Stuart Berke ,  Denis Foley

IPC: G06F15/00

CPC classification number: G06F15/17337

Abstract: There is provided a system and a method for employing multiple processors in a computer system. More specifically, there is provided a computer system comprising a first cell board including a first central processing unit, a second central processing unit, and a first data agent coupled to the first and second central processing units and configured to transmit signals from the first and second central processing units to a first crossbar circuit. There is also provided a second cell board including a third central processing unit coupled to the first central processing unit via a point-to-point data link, a fourth central processing unit, and a second data agent coupled to the third and fourth central processing units and configured to transmit signals from the third and fourth central processing units to a second crossbar circuit.

Abstract translation: 提供了一种在计算机系统中采用多个处理器的系统和方法。 更具体地，提供了一种计算机系统，包括第一单元板，其包括第一中央处理单元，第二中央处理单元和耦合到第一和第二中央处理单元的第一数据代理，并且被配置为从第一和第二中央处理单元 第二中央处理单元连接到第一横向电路。 还提供了一种第二单元板，包括经由点到点数据链路耦合到第一中央处理单元的第三中央处理单元，第四中央处理单元和耦合到第三和第四中央处理的第二数据代理 单元并且被配置为将信号从第三和第四中央处理单元传送到第二交叉电路。

公开(公告)号：US20060161718A1

公开(公告)日：2006-07-20

申请号：US11039308

申请日：2005-01-20

Applicant: Stuart Berke ,  Mark Shaw

Inventor： Stuart Berke ,  Mark Shaw

IPC: G06F13/00

CPC classification number: G06F13/4022

Abstract: A system and method for communicatively coupling a plurality of processor groups residing in a symmetric multiprocessing (SMP) system. One embodiment of a non-uniform crossbar switch plane multiprocessing (SMP) system comprises a plurality of processor groups and a non-uniform crossbar switch plane system comprising a plurality of routes, such that each of the processor groups are coupled to the other processor groups by a number of routes at most equal to (N-1), where N equals the number of processor groups.

Abstract translation: 用于通信地耦合驻留在对称多处理（SMP）系统中的多个处理器组的系统和方法。 非均匀交叉开关平面多处理（SMP）系统的一个实施例包括多个处理器组和包括多个路由的非均匀交叉开关平面系统，使得每个处理器组耦合到其他处理器组 通过多个路由最多等于（N-1），其中N等于处理器组的数量。

公开(公告)号：US20070081315A1

公开(公告)日：2007-04-12

申请号：US11214075

申请日：2005-08-29

Applicant: Robert Mondor ,  Jeffrey Lewis ,  Stuart Berke

Inventor： Robert Mondor ,  Jeffrey Lewis ,  Stuart Berke

IPC: H01R12/16

CPC classification number: G06F13/409 ,  H04Q1/03 ,  H04Q1/035 ,  H04Q1/116 ,  H04Q1/155

Abstract: An enclosure for an input-output (IO) subsystem comprises: a backplane; a plurality of first slots for accepting corresponding IO option modules; a second slot for accepting an IO controller module; a plurality of first connectors corresponding to the plurality of first slots for connecting the corresponding IO option modules to the backplane; a second connector corresponding to the second slot for connecting the IO controller module to the backplane; and wherein the backplane includes communication links for interconnecting the second connector to each of the plurality of first connectors.

Abstract translation: 用于输入 - 输出（IO）子系统的外壳包括：背板; 用于接受相应的IO选项模块的多个第一槽; 用于接收IO控制器模块的第二插槽; 对应于所述多个第一槽的多个第一连接器，用于将相应的IO选件模块连接到所述背板; 对应于第二槽的第二连接器，用于将IO控制器模块连接到背板; 并且其中所述背板包括用于将所述第二连接器互连到所述多个第一连接器中的每一个的通信链路。

公开(公告)号：US20060294317A1

公开(公告)日：2006-12-28

申请号：US11158419

申请日：2005-06-22

Applicant: Stuart Berke

Inventor： Stuart Berke

IPC: G06F13/28

CPC classification number: G06F15/16

Abstract: A symmetric multiprocessor (“SMP”) computer architecture with interchangeable processor and input/output (“IO”) modules is disclosed. In one embodiment, the computer comprises a circuit board to interconnect processor modules and IO modules that are interchangeable with each other. Each of the interchangeable modules includes a portion of a cache-coherent system memory.

Abstract translation: 公开了具有可互换处理器和输入/输出（“IO”）模块的对称多处理器（“SMP”）计算机体系结构。 在一个实施例中，计算机包括用于互连可互换的处理器模块和IO模块的电路板。 每个可互换模块包括高速缓存相干系统存储器的一部分。

公开(公告)号：US20060277422A1

公开(公告)日：2006-12-07

申请号：US11145249

申请日：2005-06-03

Applicant: Stuart Berke ,  Shane Chiasson

Inventor： Stuart Berke ,  Shane Chiasson

IPC: G06F1/26

CPC classification number: G06F1/263 ,  G11C5/141

Abstract: An information handling system (“IHS”) includes a processor, a memory module coupled to the processor, a memory device, and a power source, coupled to the memory device, for supplying power to the memory device. Also, the IHS includes a first battery, coupled to the memory device, for supplying power to the memory device, a second battery, located on the memory module and coupled to the memory device, for supplying power to the memory device, and a switching circuit coupled to the memory device, the power source, the first battery, and the second battery. The switching circuit is for, in response to determining that the power source is unavailable to supply power to the memory device, supplying power from the first battery. The switching circuit is also for, in response to determining that the power source and the first battery are unavailable to supply power to the memory device, supplying power from the second battery.

Abstract translation: 信息处理系统（“IHS”）包括耦合到处理器的存储器模块，耦合到存储器件的存储器件和电源，用于向存储器件供电。 此外，IHS包括耦合到存储器装置的用于向存储器件供电的第一电池，位于存储器模块上并耦合到存储器件的用于向存储器件供电的第二电池，以及开关 电路，耦合到存储器件，电源，第一电池和第二电池。 响应于确定电源不能向存储器件供电，开关电路用于从第一电池供电。 开关电路还用于响应于确定电源和第一电池不能向存储器件供电，从第二电池供电。

公开(公告)号：US07500115B2

公开(公告)日：2009-03-03

申请号：US11145249

申请日：2005-06-03

Applicant: Stuart Berke ,  Shane Chiasson

Inventor： Stuart Berke ,  Shane Chiasson

IPC: G06F1/00 ,  G06F11/30 ,  G06F13/00

CPC classification number: G06F1/263 ,  G11C5/141

Abstract: An information handling system (IHS) includes a processor, a memory module coupled to the processor, a memory device, and a power source, coupled to the memory device, for supplying power to the memory device. Also, the IHS includes a first battery, coupled to the memory device, for supplying power to the memory device, a second battery, located on the memory module and coupled to the memory device, for supplying power to the memory device, and a switching circuit coupled to the memory device, the power source, the first battery, and the second battery. The switching circuit is for, in response to determining that the power source is unavailable to supply power to the memory device, supplying power from the first battery. The switching circuit is also for, in response to determining that the power source and the first battery are unavailable to supply power to the memory device, supplying power from the second battery.

Abstract translation: 信息处理系统（IHS）包括处理器，耦合到处理器的存储器模块，耦合到存储器件的存储器件和电源，用于向存储器件供电。 此外，IHS包括耦合到存储器装置的用于向存储器件供电的第一电池，位于存储器模块上并耦合到存储器件的用于向存储器件供电的第二电池，以及开关 电路，耦合到存储器件，电源，第一电池和第二电池。 响应于确定电源不能向存储器件供电，开关电路用于从第一电池供电。 开关电路还用于响应于确定电源和第一电池不能向存储器件供电，从第二电池供电。

公开(公告)号：US20060174069A1

公开(公告)日：2006-08-03

申请号：US11047539

申请日：2005-01-31

Applicant: Mark Shaw ,  Stuart Berke

Inventor： Mark Shaw ,  Stuart Berke

IPC: G06F13/28

CPC classification number: G06F12/0817

Abstract: A system and method for maintaining coherency in a symmetric multiprocessing (SMP) system are disclosed. Briefly described, in architecture, one exemplary embodiment comprises a first crossbar coupled to a plurality of local processors; a second crossbar coupled to at least one remote processor; and at least one crossbar directory that tracks access of information by a remote processor in a symmetric multiprocessing (SMP) system, the remote processor in communication with at least one of the local processors via the crossbars, such that a most current location of the information can be determined by the crossbar directory.

Abstract translation: 公开了一种用于在对称多处理（SMP）系统中维持一致性的系统和方法。 简要描述，在架构中，一个示例性实施例包括耦合到多个本地处理器的第一交叉开关; 耦合到至少一个远程处理器的第二横杆; 以及至少一个交叉目录，其跟踪对称多处理（SMP）系统中的远程处理器对信息的访问，所述远程处理器经由所述交叉开关与至少一个所述本地处理器通信，使得所述信息的最新位置 可以由crossbar目录确定。

公开(公告)号：US20060143357A1

公开(公告)日：2006-06-29

申请号：US11024575

申请日：2004-12-29

Applicant: Mark Shaw ,  Russ Herrell ,  Stuart Berke

Inventor： Mark Shaw ,  Russ Herrell ,  Stuart Berke

IPC: G06F13/00

CPC classification number: G06F15/17375 ,  G06F15/8007

Abstract: In an embodiment, a multi-processor computer system includes multiple cells, where a cell may include one or more processors and memory resources. The system may further include a global crossbar network and multiple cell-to-global-crossbar connectors, to connect the multiple cells with the global crossbar network. In an embodiment, the system further includes at least one cell-to-cell connector, to directly connect at least one pair of the multiple cells. In another embodiment, the system further includes one or more local crossbar networks, multiple cell-to-local-crossbar connectors, and local input/output backplanes connected to the one or more local crossbar networks.

Abstract translation: 在一个实施例中，多处理器计算机系统包括多个小区，其中小区可以包括一个或多个处理器和存储器资源。 该系统还可以包括全局交叉网络和多个小区到全局交叉连接器，以将多个小区与全局交叉网络连接。 在一个实施例中，系统还包括至少一个单元到单元连接器，以直接连接至少一对多个单元。 在另一个实施例中，该系统还包括一个或多个本地交叉网络，多个小区到本地交叉连接器以及连接到一个或多个本地交叉网络的本地输入/输出背板。