公开(公告)号：US20220310835A1

公开(公告)日：2022-09-29

申请号：US17612542

申请日：2020-05-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Takashi ICHIRYU ,  Yusuke KINOSHITA ,  Ryusuke KANOMATA ,  Masanori NOMURA ,  Hidetoshi ISHIDA

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205

Abstract: A bidirectional switch module includes a plurality of bidirectional switches and a mount board. Each of the plurality of bidirectional switches includes a first source electrode, a first gate electrode, a second gate electrode, and a second source electrode. On the mount board, the plurality of bidirectional switches are mounted. In the bidirectional switch module, the plurality of bidirectional switches are connected in parallel.

公开(公告)号：US20250030345A1

公开(公告)日：2025-01-23

申请号：US18713089

申请日：2022-09-27

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Ryusuke KANOMATA ,  Shinji UJITA ,  Kenichiro TANAKA ,  Takeshi NAKAYASHIKI ,  Takayuki HIROKAWA

IPC: H02M3/158 ,  H02M1/00 ,  H02M7/44

Abstract: The power conversion device can undergo autonomous search control for ZVS without a larger circuit area or lower reliability. The power conversion device performs, in each switching cycle, an operation of turning the control switch (CTLSW) on and afterward off while the synchronous rectification switch (SRSW) is off, and then turning the synchronous rectification switch on and afterward off while the control switch is off. Whether the inductor current (iL) is positive or negative is detected at the detection timing backed by a predetermined period (Text) from a timing at which the synchronous rectification switch switches from on to off, based on the detection result, the on-period (TOFF) of the synchronous rectification switch is corrected.

公开(公告)号：US20220224321A1

公开(公告)日：2022-07-14

申请号：US17614716

申请日：2020-04-28

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yusuke KINOSHITA ,  Takashi ICHIRYU ,  Ryusuke KANOMATA ,  Hidetoshi ISHIDA

IPC: H03K17/04

Abstract: A speed-up circuit is configured to be provided between a power supply terminal and a gate of a semiconductor switching element. An impedance element is configured to be provided between a signal input terminal and a node, the node being between the speed-up circuit and the gate of the semiconductor switching element. In the speed-up circuit, a second field effect transistor is connected in series to a first field effect transistor and is configured to be connected to the gate of the semiconductor switching element. The impedance element has an impedance higher than an impedance of the speed-up circuit when both the first field effect transistor and the second field effect transistor are in an ON state.