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公开(公告)号：US09374070B2
公开(公告)日：2016-06-21
申请号：US14552446
申请日：2014-11-24
Inventor： Masahiro Higuchi , Hiroshi Fujinaka , Makoto Ikuma
IPC: H03K4/90 , H04N5/357 , H04N5/378 , H03K4/08 , H01L27/146
CPC classification number: H03K4/90 , H01L27/14645 , H03K4/08 , H04N5/357 , H04N5/378
Abstract: A ramp generator circuit includes: a reference signal generator circuit which generates a ramp waveform having a slope obtained by multiplication using a power of 2 according to a value of a higher order bit of a gain control signal; a clock control circuit which selectively outputs 2^m kinds of fractional-N clocks according to one of 2^m (natural number) areas obtained by dividing a code range represented by a lower order bit, when a negative gain is set; and a variable gain circuit which sets a ramp waveform according to the value of the gain control signal, and sets a ramp signal amplitude in each area so that a period ratio between ramp driving clocks for adjacent areas and a ratio between an amplitude of a ramp signal when the standard gain is set and a largest amplitude of a ramp signal are equal.
Abstract translation: 斜坡发生器电路包括：参考信号发生器电路，其产生具有根据增益控制信号的较高阶位的值使用2的幂乘以获得的斜率的斜坡波形; 时钟控制电路，当设置负增益时，根据通过划分由低位位表示的代码范围获得的2 ^ m（自然数）区域中的一个选择性地输出2 ^ m种分数N个时钟; 以及可变增益电路，其根据增益控制信号的值设定斜坡波形，并且设置每个区域中的斜坡信号振幅，使得相邻区域的斜坡驱动时钟之间的周期比和斜坡幅度之间的比率 当标准增益被设置并且斜坡信号的最大振幅相等时发出信号。
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公开(公告)号：US10778921B2
公开(公告)日：2020-09-15
申请号：US16491555
申请日：2018-02-27
Inventor： Yutaka Abe , Kazuko Nishimura , Hiroshi Fujinaka , Masahiro Higuchi , Dai Ichiryu
IPC: H04N5/374 , H04N5/3745 , H03M1/38 , H03M1/56 , H04N5/378
Abstract: A solid-state imaging device includes an A/D converter per column. The A/D converter performs a first A/D conversion that (i) refines, using a first comparator, a range including a potential of an analog signal to a range of a potential corresponding to a difference between a first potential and a second potential through a binary search, and further (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of a digital signal. The A/D converter also performs a second A/D conversion that generates, based on a ramp signal and the result of the binary search, a second digital signal being a low-order portion of a remainder of the digital signal, by measuring a time necessary for an output of a second comparator to be inverted.
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公开(公告)号：US09549135B2
公开(公告)日：2017-01-17
申请号：US14858481
申请日：2015-09-18
Inventor： Takayasu Kito , Hiroyuki Amikawa , Masahiro Higuchi , Kenichi Origasa , Hiroshi Fujinaka
IPC: H04N5/374 , H04N5/3745 , H04N5/369 , H04N5/357 , H04N5/378
CPC classification number: H04N5/374 , H04N5/3577 , H04N5/3698 , H04N5/3745 , H04N5/378
Abstract: A solid-state imaging device includes: a plurality of unit cells each including at least one light receiving unit and an amplifying transistor which outputs an amplified signal corresponding to an amount of the signal charge photoelectrically converted by the light receiving unit; a plurality of vertical signal lines each for receiving an output signal from the amplifying transistor; a pixel power supply line for supplying a power supply voltage to the amplifying transistor; a plurality of constant current source transistors each connected to a different one of the vertical signal lines; and a bias circuit which controls an amount of current to be supplied to each of the constant current source transistors, based on a variation in the power supply voltage.
Abstract translation: 固态成像装置包括：多个单位电池，每个单元电池包括至少一个光接收单元和放大晶体管，其输出对应于由光接收单元光电转换的信号电荷的量的放大信号; 多个垂直信号线，各自用于接收来自放大晶体管的输出信号; 用于向放大晶体管提供电源电压的像素电源线; 多个恒流源晶体管，每个连接到所述垂直信号线中的不同的一个; 以及偏置电路，其基于电源电压的变化来控制要提供给每个恒流源晶体管的电流量。
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公开(公告)号：US10931908B2
公开(公告)日：2021-02-23
申请号：US16491123
申请日：2018-02-27
Inventor： Yutaka Abe , Kazuko Nishimura , Hiroshi Fujinaka , Norihiko Sumitani , Yosuke Higashi
Abstract: A solid-state imaging device includes a first A/D converter circuit and a second A/D converter circuit per column. The first A/D converter circuit performs a first A/D conversion that (i) refines, using a first comparator, a range including a potential of an analog signal through a binary search, and (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of the digital signal. The second A/D converter circuit performs a second A/D conversion that generates a second digital signal being a low-order portion that is a remainder of the digital signal by measuring a time required for an output of the second comparator to be inverted, the second comparator comparing a quantitative relationship between the analog signal refined and a ramp signal.
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