公开(公告)号：US09654063B2

公开(公告)日：2017-05-16

申请号：US14885671

申请日：2015-10-16

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yukio Okazaki ,  Masakatsu Maeda ,  Shigeki Nakamura ,  Akinori Daimo

IPC: H03F3/04 ,  H03F3/193 ,  H03F1/02 ,  H03F3/24 ,  H03F1/30

CPC classification number: H03F3/193 ,  H03F1/0261 ,  H03F1/301 ,  H03F3/245 ,  H03F2200/18 ,  H03F2200/27 ,  H03F2200/451 ,  H03F2200/453 ,  H03F2200/541 ,  H03F2200/555

Abstract: A bias circuit comprises: a first circuit that comprises a first resistor and a decoupling capacitor; a bias voltage generation circuit that comprises a first transistor being connected to the first circuit; one or more switches; a first replica circuit comprising a second circuit and a second transistor, the second circuit comprising a second resistor and a capacitor, the second transistor being connected to the second circuit; a second replica circuit comprising a third transistor; a comparator that makes a comparison between a pseudo-bias voltage and a reference voltage; and a control circuit that controls the one or more switches on the basis of the comparison result to reduce the amount of the current flowing through the first transistor.