公开(公告)号：US20240290759A1

公开(公告)日：2024-08-29

申请号：US18582905

申请日：2024-02-21

Applicant: POWER MASTER SEMICONDUCTOR CO., LTD.

Inventor： Taekkeun LEE ,  In-Suk KIM ,  Ki-Myung YOON ,  Jooyaung EOM ,  Soonho KWON

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/373

CPC classification number: H01L25/072 ,  H01L23/3735 ,  H01L24/40 ,  H01L24/48 ,  H01L2224/40139 ,  H01L2224/48139

Abstract: Provided is a semiconductor device. A semiconductor device is implemented as a semiconductor module package for driving an inverter, the semiconductor device may include: a first upper metal layer in which a plurality of first semiconductor chips implementing a switching pattern of a low voltage phase are disposed along a first row in a first direction; a first connection connecting the plurality of first semiconductor chips in series and extending to a second upper metal layer; and a first lead frame providing power to the semiconductor device from an external source through the second upper metal layer, wherein, in the second upper metal layer, a first vertically extending leg portion and a second vertically extending leg portion of the first lead frame forming a fork shape are disposed, and the first connection is disposed between the first vertically extending leg portion and the second vertically extending leg portion.

公开(公告)号：US20240213126A1

公开(公告)日：2024-06-27

申请号：US18544774

申请日：2023-12-19

Applicant: POWER MASTER SEMICONDUCTOR CO., LTD.

Inventor： Jooyaung EOM ,  In-Suk KIM ,  Ki-Myung YOON ,  Taekkeun LEE ,  Soonho KWON

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367

CPC classification number: H01L23/49568 ,  H01L23/3121 ,  H01L23/3675 ,  H01L23/49537 ,  H01L23/49562 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/40175 ,  H01L2224/48175 ,  H01L2224/73221 ,  H01L2924/182

Abstract: A semiconductor device is provided. The semiconductor device may include a heat dissipation pad that is formed such that the upper surface is exposed to the outside of a molding portion, a first lead frame that is formed on the left side of the heat dissipation pad so as to be spaced apart from the heat dissipation pad and includes a first portion extending in an upward and downward direction and a second portion protruding in a right direction, second lead frames that are formed on the right side of the heat dissipation pad, a first connection part that is formed so as to be connected to both of the lower surface of the heat dissipation pad and the lower surface of the second portion of the first lead frame, a semiconductor chip that is formed on the lower surface of the heat dissipation pad, and a second connection part that connects the semiconductor chip and the second lead frames.

公开(公告)号：US20240222255A1

公开(公告)日：2024-07-04

申请号：US18396011

申请日：2023-12-26

Applicant: POWER MASTER SEMICONDUCTOR CO., LTD.

Inventor： Jooyaung EOM ,  In-Suk KIM ,  Ki-Myung YOON ,  Taekkeun LEE ,  Soonho KWON

IPC: H01L23/498

CPC classification number: H01L23/49861 ,  H01L23/49844

Abstract: Provided is a semiconductor device. A semiconductor device may include: an insulated substrate whose upper surface is exposed to an outside of a molding portion; a semiconductor chip formed on a lower surface of the insulated substrate; a drain connection lead, one part of which forming a junction extending along a first direction or a second direction perpendicular to the first direction on the lower surface of the insulated substrate, and the other part of which forming a terminal that can be connected to an external device; and a source connection lead, one part of which forming an electrical connection with the semiconductor chip through a connection, and the other part of which forming a terminal that can be connected to an external device.

公开(公告)号：US20240213208A1

公开(公告)日：2024-06-27

申请号：US18396035

申请日：2023-12-26

Applicant: POWER MASTER SEMICONDUCTOR CO., LTD.

Inventor： Taekkeun LEE ,  In-Suk KIM ,  Ki-Myung YOON ,  Jooyaung EOM ,  Soonho KWON

IPC: H01L23/00 ,  H01L23/373 ,  H01L25/07

CPC classification number: H01L24/37 ,  H01L23/3735 ,  H01L24/40 ,  H01L25/072 ,  H01L2224/37005 ,  H01L2224/40139 ,  H01L2224/40225

Abstract: Provided is a semiconductor device. A semiconductor device is implemented as a semiconductor module package for driving an inverter, the semiconductor device may include: a first upper metal layer in which a plurality of semiconductor chips implementing a right phase switching pattern are disposed along a first direction to form a first row; a second upper metal layer in which a plurality of semiconductor chips implementing a left phase switching pattern are disposed along the first direction to form a second row; a first connection, in the first upper metal layer, connecting a plurality of semiconductor chips disposed along the first row to each other in series and to the second upper metal layer in parallel; and a second connection, in the second upper metal layer, connecting a plurality of semiconductor chips disposed along the second row to each other in series.

公开(公告)号：US20240014106A1

公开(公告)日：2024-01-11

申请号：US18218182

申请日：2023-07-05

Applicant: POWER MASTER SEMICONDUCTOR CO., LTD.

Inventor： Jooyaung EOM ,  Ki-Myung YOON ,  Taekkeun LEE ,  Soonho KWON

IPC: H01L23/495 ,  H01L23/373 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49551 ,  H01L23/3736 ,  H01L23/49537 ,  H01L23/49568 ,  H01L25/0655 ,  H01L24/32 ,  H01L2224/32245 ,  H01L2924/37001

Abstract: Provided is a semiconductor device. A semiconductor device may include: a substrate formed to extend along a first direction; a first semiconductor chip formed on the substrate; a second semiconductor chip formed on the substrate at a predetermined distance from the first semiconductor chip along the first direction; a first lead frame extending outwardly beyond the substrate along the first direction, the first lead frame having a lower surface connected to upper surfaces of each of the first semiconductor chip and the second semiconductor chip; and a heat sink formed at a position corresponding to the first semiconductor chip and the second semiconductor chip on the first lead frame, wherein the first lead frame includes a first groove region formed between a region on the lower surface connected to the upper surface of the first semiconductor chip and a region on the lower surface connected to the upper surface of the second semiconductor chip.