-
公开(公告)号：US20240396344A1
公开(公告)日：2024-11-28
申请号：US18493683
申请日：2023-10-24
Inventor： Jae Yoon SIM , Hee Sung ROH
Abstract: Disclosed is an energy harvesting method of an energy harvesting apparatus configured to convert input power coming from an energy source using a switching frequency, which is generated by monitoring an input voltage, and a first time and a second time, which are on-times of a first switch and a second switch, respectively, and generated based on the switching frequency, and deliver the converted input power to a battery.
-
公开(公告)号：US20250045617A1
公开(公告)日：2025-02-06
申请号：US18786131
申请日：2024-07-26
Inventor： Jae Yoon SIM , Dong Gyu MINN
IPC: G06N10/40
Abstract: Provided is a qubit state reading apparatus including a probe signal provider configured to provide a probe signal to a qubit and a readout module configured to receive a qubit signal output from the qubit to which the probe signal is provided and read a state of the qubit, in which the readout module includes a local oscillation (LO) signal generator configured to generate an LO signal, a mixer configured to down-convert the qubit signal using the LO signal, an accumulator configured to accumulate output signals of the mixer, and a comparator configured to compare an output signal of the accumulator with a threshold and output a signal corresponding to the state of the qubit, and the readout module down-converts the qubit signal and the LO signal in a homodyne manner.
-
Patent Agency Ranking
公开(公告)号：US20240283403A1
公开(公告)日：2024-08-22
申请号：US18582307
申请日：2024-02-20
Inventor： Jae Yoon SIM , Young Woo JI
IPC: H03B5/04 , H03K3/011 , H03K3/0231
CPC classification number: H03B5/04 , H03K3/011 , H03K3/0231
Abstract: Disclosed an oscillator circuit device includes: a resistor circuit comprising a first resistor disposed between a first supply voltage level and an output node; a resistor-capacitor circuit comprising a second resistor and at least one capacitor disposed between the output node and a second supply voltage level and connected in series, and a switch capable of discharging electric charges accumulated in the at least one capacitor; and a comparator configured to compare a voltage level to be compared obtained from the resistor circuit with a predetermined reference to allow the switch to be opened and closed according to a comparison result.
-
公开(公告)号：US20250094851A1
公开(公告)日：2025-03-20
申请号：US18542385
申请日：2023-12-15
Inventor： Seok Hyeong KANG , Sung Hye PARK , Jae Yoon SIM , Do Hun KIM
Abstract: Disclosed is a multi-constraint qubit allocation method and a quantum apparatus using the same. The method comprises generating an interaction graph representing a quantum circuit on the basis of the number of two-qubit gates, determining edge weights between connected nodes in the interaction graph by introducing a fitting coefficient for a decay effect, searching for an isomorphic part, layout graph, between target hardware and the interaction graph by graph matching, and performing frequency matching for a layout graph by searching for frequency allocated to each location of qubits by limiting unidirectional movement on each of an x-axis and a y-axis of a hardware plane of the target hardware to a range from −1 to +1.
-
公开(公告)号：US20230318829A1
公开(公告)日：2023-10-05
申请号：US18190922
申请日：2023-03-27
Inventor： Jae Yoon SIM , Byung Jun KIM
CPC classification number: H04L9/3093 , H04L9/0852
Abstract: The present disclosure provides a cryptographic processor device capable of performing the post-quantum cryptographic encryption with in a high speed with low power, allowing a change of encryption parameters, and handling various cryptographic protocols. The cryptographic processor device executing polynomial vector operations required for a post-quantum cryptography includes: a polynomial memory bank configured to store a plurality of polynomial vectors; and an arithmetic and logic operator configured to perform operation on the polynomial vectors. The arithmetic and logic operator includes a transform operation circuit configured to multiply two polynomial vectors read out from the polynomial memory bank by using a predetermined transform operation including a plurality of operation stages, and including a combined operation unit configured to consecutively perform a first stage operation and a second stage operation among the plurality of operation stages without storing a result of the first operation stage in a memory.
-
公开(公告)号：US20230044357A1
公开(公告)日：2023-02-09
申请号：US17736986
申请日：2022-05-04
Inventor： Jae Han PARK , Jae Yoon SIM
IPC: H04L9/08 , H03K19/003
Abstract: An exemplary embodiment of the present disclosure provides a physically unclonable function (PUF) cell capable of exhibiting a stable performance and showing an excellent repeatability while being less affected by environmental factors such as a noise, temperature, and bias voltage. The PUF cell generates an output value by combining a scheme of amplifying a threshold voltage difference and a scheme of amplifying an oscillation frequency difference. In an oscillator that generates oscillation signals of different frequencies, the frequency difference of the oscillation signals is amplified by alternately supplying bias voltages of different magnitudes generated by utilizing the threshold voltage difference to a plurality of stages in the oscillator.
-
公开(公告)号：US20220209755A1
公开(公告)日：2022-06-30
申请号：US17560090
申请日：2021-12-22
Inventor： Jae Yoon SIM , Ki Seo KANG
Abstract: The present disclosure provides a device and method of generating a nonlinear waveform signal dissipating low power and operating at a high speed. The device includes: a digital preprocessing unit configured to quantize an effective input signal to generate a linear data signal and a residual signal that is a difference between the effective input signal and the linear data signal; a nonlinear digital-to-analog conversion circuit (DAC) having a nonlinear relationship between an input and an output and configured to convert the linear data signal into a first analog signal; a linear interpolation DAC configured to convert the residual signal into a second analog signal to enable a generation of a converted analog signal by an addition of the second analog signal to the first analog signal; and an output circuit configured to output the converted analog signal as a nonlinear waveform signal.
-
-
-
-
-
-
Search Results
7
records
(took 0.019 seconds)
