公开(公告)号：US20200026323A1

公开(公告)日：2020-01-23

申请号：US16474524

申请日：2017-11-30

Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATION

Inventor： Jae Yoon SIM ,  Hwa Suk CHO

IPC: G06F1/03 ,  H03L7/081 ,  H03L7/083 ,  H03L7/197

Abstract: The present invention relates to a design technology of a phase locked loop (PLL) for generating an accurate clock frequency in a clock synchronization system.The present invention suggests a new structure based on a hardware description language (HDL), and thus reduces a chip area of a frequency synthesizer while obtaining a wide frequency operation range.Furthermore, since only the HDL is used, the entire frequency synthesizer becomes all-synthesizable, and auto layout (auto P&R) can be achieved through a tool, which makes it possible to reduce a design cost of a designer.

公开(公告)号：US20190279079A1

公开(公告)日：2019-09-12

申请号：US16276452

申请日：2019-02-14

Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATION

Inventor： Jae Yoon SIM ,  Hwa Suk CHO ,  Hyun Woo SON

IPC: G06N3/063 ,  G06N3/08 ,  G06N20/00 ,  G06F1/03

Abstract: Provided is a technology for reducing hardware cost and enabling on-chip learning in a neuromorphic system. A synapse array includes a plurality of synapse circuits, and at least one of the plurality of synapse circuits includes at least bias transistor and a switch connected in series. Synapse circuits in the same row and column direction of the synapse array are connected to each other through a shared membrane line, and a charge amount proportional to a multiplication accumulation operation required for a forward or backward operation is supplied through the membrane line and is converted into a final digital value for output through an analog to digital converter. A virtual look-up table performs in advance a calculation required for a synapse weight update for learning of at least one column of the synapse array and is updated, so that the amount of a calculation required for entire learning is reduced.