公开(公告)号：US20200326736A1

公开(公告)日：2020-10-15

申请号：US16427289

申请日：2019-05-30

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jia-Huei Yeh ,  Chao-Ta Huang ,  Yi-Feng Li ,  Po-Chieh Chiu ,  Chun-Yu Ling

IPC: G05D23/24 ,  H01L23/34 ,  G01R31/28 ,  G05D23/19

Abstract: A temperature control circuit for an electronic device is provided. The temperature control circuit includes a temperature detector, a status detection circuit and a control circuit. The temperature detector is configured to detect a temperature of the electronic device and generate first evaluation information. The status detection circuit is configured to detect a work status of at least one circuit module in the electronic device and generate second evaluation information. The control circuit is configured to adjust at least one electronic parameter of the electronic device according to the first evaluation parameter and the second evaluation parameter to control the temperature of the electronic device.

公开(公告)号：US11635777B2

公开(公告)日：2023-04-25

申请号：US16427289

申请日：2019-05-30

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jia-Huei Yeh ,  Chao-Ta Huang ,  Yi-Feng Li ,  Po-Chieh Chiu ,  Chun-Yu Ling

IPC: G05D23/24 ,  G05D23/19 ,  G01R31/28 ,  H01L23/34

Abstract: A temperature control circuit for an electronic device is provided. The temperature control circuit includes a temperature detector, a status detection circuit and a control circuit. The temperature detector is configured to detect a temperature of the electronic device and generate first evaluation information. The status detection circuit is configured to detect a work status of at least one circuit module in the electronic device and generate second evaluation information. The control circuit is configured to adjust at least one electronic parameter of the electronic device according to the first evaluation parameter and the second evaluation parameter to control the temperature of the electronic device.

公开(公告)号：US11003460B2

公开(公告)日：2021-05-11

申请号：US15690215

申请日：2017-08-29

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Fu Lai ,  Ying-Fu Chao ,  Chao-Ta Huang ,  Chun-Yu Ling

IPC: G06F9/4401 ,  G06F9/445 ,  G06F11/14 ,  G06F12/16 ,  G11C16/08 ,  G11C16/20 ,  G11C16/22

Abstract: A control method of a memory storage device is provided and includes: detecting a first signal stream controlled by a host system; executing a boot code according to the first signal stream and entering a boot code mode; and receiving a command from the host system in the boot code mode and not executing a firmware code stored in a rewritable non-volatile memory module in the memory storage device. According, operational flexibility of the memory storage device may be enhanced.

公开(公告)号：US11334290B2

公开(公告)日：2022-05-17

申请号：US16820733

申请日：2020-03-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yi-Feng Li ,  Chao-Ta Huang ,  Chun-Yu Ling ,  Jia-Huei Yeh

IPC: G06F13/42 ,  G06F3/06

Abstract: A management method for managing a memory storage device compatible with a PCIe (PCI Express) standard is disclosed. The memory storage device has a plurality of pins configured to couple to a host system. The management method includes: transmitting a first command to the memory storage device through at least one first pin among the pins to control the memory storage device to enter a target link status; and when the memory storage device is in the target link status, transmitting a second command to the memory storage device through a second pin among the pins to control the memory storage device to leave the target link status. The second pin is not a pin dedicated to control the memory storage device to enter or leave the target link status.

公开(公告)号：US20210263680A1

公开(公告)日：2021-08-26

申请号：US16820733

申请日：2020-03-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yi-Feng Li ,  Chao-Ta Huang ,  Chun-Yu Ling ,  Jia-Huei Yeh

IPC: G06F3/06 ,  G06F13/42

Abstract: A management method for managing a memory storage device compatible with a PCIe (PCI Express) standard is disclosed. The memory storage device has a plurality of pins configured to couple to a host system. The management method includes: transmitting a first command to the memory storage device through at least one first pin among the pins to control the memory storage device to enter a target link status; and when the memory storage device is in the target link status, transmitting a second command to the memory storage device through a second pin among the pins to control the memory storage device to leave the target link status. The second pin is not a pin dedicated to control the memory storage device to enter or leave the target link status.

公开(公告)号：US20190012180A1

公开(公告)日：2019-01-10

申请号：US15690215

申请日：2017-08-29

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Fu Lai ,  Ying-Fu Chao ,  Chao-Ta Huang ,  Chun-Yu Ling

IPC: G06F9/44 ,  G11C16/08 ,  G11C16/22 ,  G06F12/16 ,  G06F9/445

Abstract: A control method of a memory storage device is provided and includes: detecting a first signal stream controlled by a host system; executing a boot code according to the first signal stream and entering a boot code mode; and receiving a command from the host system in the boot code mode and not executing a firmware code stored in a rewritable non-volatile memory module in the memory storage device. According, operational flexibility of the memory storage device may be enhanced.