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公开(公告)号:US10942680B2
公开(公告)日:2021-03-09
申请号:US16503593
申请日:2019-07-04
Applicant: PHISON ELECTRONICS CORP.
Inventor: Ping-Chuan Lin , Yi-Hsuan Lin , Bing-Hong Wu
Abstract: A data writing method, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving a first data and writing the first data to at least one first physical programming unit of a first physical erasing unit; receiving a second data; temporarily storing the second data to a temporary storage area if a data length of the second data is less than a predefined value; receiving a third data; writing the third data to at least one second physical programming unit of the first physical erasing unit if a logical address storing the first data is consecutive with a logical address storing the third data; and moving the second data from the temporary storage area to at least one second physical programming unit of the first physical erasing unit if the logical address storing the first data is not consecutive with the logical address storing the third data.
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公开(公告)号:US20200371712A1
公开(公告)日:2020-11-26
申请号:US16503593
申请日:2019-07-04
Applicant: PHISON ELECTRONICS CORP.
Inventor: Ping-Chuan Lin , Yi-Hsuan Lin , Bing-Hong Wu
Abstract: A data writing method, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving a first data and writing the first data to at least one first physical programming unit of a first physical erasing unit; receiving a second data; temporarily storing the second data to a temporary storage area if a data length of the second data is less than a predefined value; receiving a third data; writing the third data to at least one second physical programming unit of the first physical erasing unit if a logical address storing the first data is consecutive with a logical address storing the third data; and moving the second data from the temporary storage area to at least one second physical programming unit of the first physical erasing unit if the logical address storing the first data is not consecutive with the logical address storing the third data.
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