公开(公告)号：US09405690B2

公开(公告)日：2016-08-02

申请号：US13961417

申请日：2013-08-07

申请人： Oracle International Corporation

发明人： Mark A Luttrell

IPC分类号： G06F12/08

CPC分类号： G06F12/084 ,  G06F12/0811 ,  G06F12/0864

摘要： A processor may include a cache configured to store instructions and memory data for the processor. The cache may store instructions in which a relative address, such as for a branch instruction has been calculated, such that the instruction stored in the cache is modified from how the instruction is stored in main memory. The cache may include additional information in the tag to identify an instruction entry versus a memory data entry. When receiving a cache request, the cache may look at a type tag in addition to an address tag to determine if the request is a hit or a miss based upon the request being for an instruction from an instruction fetch unit or for memory data from a memory management unit. A cache entry may be invalidated and evicted if the address matches but the data type does not match.

摘要翻译： 处理器可以包括被配置为存储处理器的指令和存储器数据的高速缓存。 高速缓存可以存储其中已经计算了诸如用于分支指令的相对地址的指令，使得存储在高速缓存中的指令被修改为如何将指令存储在主存储器中。 高速缓存可以包括标签中的附加信息以识别指令条目与存储器数据条目。 当接收到缓存请求时，除了地址标签之外，高速缓存还可以查看类型标签，以根据来自指令获取单元的指令的请求或来自指令提取单元的存储器数据来确定请求是否是命中或未命中 内存管理单元。 如果地址匹配但数据类型不匹配，则缓存条目可能无效并被驱逐。