COMPUTING SYSTEM
    3.
    发明公开
    COMPUTING SYSTEM 审中-公开

    公开(公告)号:US20240272872A1

    公开(公告)日:2024-08-15

    申请号:US18569383

    申请日:2021-06-21

    IPC分类号: G06F7/57

    CPC分类号: G06F7/57

    摘要: A computing system includes a first computer for writing an arithmetic circuit in a reconfigurable first region included in a first accelerator and a second computer for writing the arithmetic circuit in a reconfigurable second region included in a second accelerator different from the first accelerator and having the same circuit arrangement as the first region. When the first computer writes a new arithmetic circuit in the first region, the second computer writes the new arithmetic circuit in a partial region of the second region at the same position as the unwritten partial region of the first region. The first computer does not write the new arithmetic circuit in the first region when the new arithmetic circuit is not normally written, and writes the new arithmetic circuit in the unwritten partial region of the first region when the new arithmetic circuit is normally written.

    NEURAL ARCHITECTURE SEARCH SYSTEM AND SEARCH METHOD

    公开(公告)号:US20230385603A1

    公开(公告)日:2023-11-30

    申请号:US18249723

    申请日:2020-11-12

    IPC分类号: G06N3/04 G06N3/08

    CPC分类号: G06N3/04 G06N3/08

    摘要: A neural architecture search system includes a deployment constraint management unit that converts a first constraint condition that defines a constraint of a system that implements a neural network into a second constraint condition that defines a constraint of a parameter that prescribes an architecture of the neural network, a learning engine unit that performs learning of the neural network under a search condition and calculates inference accuracy in a case where the learned neural network is used, and a model modification unit that causes the learning engine unit to perform the learning and the calculation of the inference accuracy while changing the architecture of the neural network on the basis of the inference accuracy and the second constraint condition so as to obtain the best inference accuracy.

    Transfer Processing Device
    8.
    发明公开

    公开(公告)号:US20240045674A1

    公开(公告)日:2024-02-08

    申请号:US18254974

    申请日:2020-12-10

    IPC分类号: G06F9/30

    CPC分类号: G06F9/3001 G06F9/30123

    摘要: A transfer processing device includes an arithmetic instruction number acquisition circuit, a buffer circuit, a transfer information acquisition circuit, and a software processing unit. The arithmetic instruction number acquisition circuit acquires a transfer instruction number corresponding to transfer information which is information related to the next transfer destination of an arithmetic instruction. The buffer circuit is arranged between the arithmetic instruction number acquisition circuit and the transfer information acquisition circuit, and temporarily stores and relays the arithmetic instruction and the arithmetic instruction number supplied from the arithmetic instruction number acquisition circuit to the transfer information acquisition circuit. The transfer information acquisition circuit acquires transfer information on the basis of the arithmetic instruction number, and gives the acquired transfer information to the arithmetic instruction. The buffer circuit holds the arithmetic instruction number and the arithmetic instruction until an output request from the transfer information acquisition circuit is received.