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1.
公开(公告)号:US11201721B2
公开(公告)日:2021-12-14
申请号:US17174787
申请日:2021-02-12
发明人: Mitsuteru Yoshida , Yasuyuki Endoh , Katsuichi Oyama , Masayuki Ikeda , Tsutomu Takeya , Etsushi Yamazaki , Yoshiaki Kisaka , Masahito Tomizawa
IPC分类号: H04B10/00 , H04L7/00 , H04B10/61 , H04B10/556
摘要: A frame synchronization apparatus (10) according to this invention includes a multiplication unit (11) configured to multiply a received signal by an inverse complex number of a predetermined synchronization pattern with respect to a predetermined signal point on a complex space diagram for each of a plurality of symbols of the received signal, an addition average unit (12) configured to perform addition averaging of outputs from the multiplication unit for the plurality of symbols of the received signal, and a synchronization determination unit (13) configured to perform coincidence determination of whether an output from the addition average unit (12) falls within a predetermined coincidence determination range of the predetermined signal point, and determine a synchronization state of the frame synchronization based on a result of the coincidence determination. According to this invention, it is possible to provide a frame synchronization apparatus that correctly determines a synchronization state even if an error rate of received symbols is high.
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公开(公告)号:US20240004828A1
公开(公告)日:2024-01-04
申请号:US18251123
申请日:2020-11-11
发明人: Kenji Tanaka , Tsuyoshi Ito , Yuki Arikawa , Tsutomu Takeya , Kazuhiko Terada , Takeshi Sakamoto
IPC分类号: G06F15/173 , G06F9/38
CPC分类号: G06F15/17306 , G06F9/3867
摘要: Each NIC performs an aggregation calculation of data output from each processor in a normal order including a head NIC located at a head position of a first pipeline connection, an intermediate NIC located at an intermediate position, and a tail NIC located at a tail position, and when the aggregation calculation in the tail NIC is completed, each NIC starts distribution of an obtained aggregation result, distributes the aggregation result in a reverse order including the tail NIC, the intermediate NIC, and the head NIC, and outputs the aggregation result to the processor of the communication interface.
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公开(公告)号:US20240272872A1
公开(公告)日:2024-08-15
申请号:US18569383
申请日:2021-06-21
发明人: Tsuyoshi Ito , Yuki Arikawa , Tsutomu Takeya , Kenji Tanaka
IPC分类号: G06F7/57
CPC分类号: G06F7/57
摘要: A computing system includes a first computer for writing an arithmetic circuit in a reconfigurable first region included in a first accelerator and a second computer for writing the arithmetic circuit in a reconfigurable second region included in a second accelerator different from the first accelerator and having the same circuit arrangement as the first region. When the first computer writes a new arithmetic circuit in the first region, the second computer writes the new arithmetic circuit in a partial region of the second region at the same position as the unwritten partial region of the first region. The first computer does not write the new arithmetic circuit in the first region when the new arithmetic circuit is not normally written, and writes the new arithmetic circuit in the unwritten partial region of the first region when the new arithmetic circuit is normally written.
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公开(公告)号:US20240184965A1
公开(公告)日:2024-06-06
申请号:US18554287
申请日:2021-04-28
发明人: Yuki Arikawa , Kenji Tanaka , Tsuyoshi Ito , Tsutomu Takeya , Takeshi Sakamoto
IPC分类号: G06F30/337 , G06F119/02
CPC分类号: G06F30/337 , G06F2119/02
摘要: A calculation resource control device includes an input unit to which a processing content specified by a user is input, an equivalent circuit preparation unit that collects candidates for an equivalent circuit that is a processing circuit having a function of executing a part of the processing content to output an equivalent circuit candidate group, and a function chain creation unit that determining a processing execution circuit from the equivalent circuit candidate group on the basis of a predetermined reference, determines a connection order of the processing execution circuit, and outputs a function chain for executing the processing content.
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公开(公告)号:US20230385603A1
公开(公告)日:2023-11-30
申请号:US18249723
申请日:2020-11-12
发明人: Yuki Arikawa , Kenji Tanaka , Tsuyoshi Ito , Tsutomu Takeya , Takeshi Sakamoto
摘要: A neural architecture search system includes a deployment constraint management unit that converts a first constraint condition that defines a constraint of a system that implements a neural network into a second constraint condition that defines a constraint of a parameter that prescribes an architecture of the neural network, a learning engine unit that performs learning of the neural network under a search condition and calculates inference accuracy in a case where the learned neural network is used, and a model modification unit that causes the learning engine unit to perform the learning and the calculation of the inference accuracy while changing the architecture of the neural network on the basis of the inference accuracy and the second constraint condition so as to obtain the best inference accuracy.
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6.
公开(公告)号:US11323238B2
公开(公告)日:2022-05-03
申请号:US16972531
申请日:2019-06-06
发明人: Mitsuteru Yoshida , Yasuyuki Endoh , Katsuichi Oyama , Masayuki Ikeda , Tsutomu Takeya , Etsushi Yamazaki , Yoshiaki Kisaka , Masahito Tomizawa
IPC分类号: H04L7/00 , H04L7/04 , H04L27/227 , H04B10/556 , H04B10/61
摘要: A frame synchronization apparatus (10) according to this invention includes a multiplication unit (11) configured to multiply a received signal by an inverse complex number of a predetermined synchronization pattern with respect to a predetermined signal point on a complex space diagram for each of a plurality of symbols of the received signal, an addition average unit (12) configured to perform addition averaging of outputs from the multiplication unit for the plurality of symbols of the received signal, and a synchronization determination unit (13) configured to perform coincidence determination of whether an output from the addition average unit (12) falls within a predetermined coincidence determination range of the predetermined signal point, and determine a synchronization state of the frame synchronization based on a result of the coincidence determination. According to this invention, it is possible to provide a frame synchronization apparatus that correctly determines a synchronization state even if an error rate of received symbols is high.
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公开(公告)号:US12056082B2
公开(公告)日:2024-08-06
申请号:US18251123
申请日:2020-11-11
发明人: Kenji Tanaka , Tsuyoshi Ito , Yuki Arikawa , Tsutomu Takeya , Kazuhiko Terada , Takeshi Sakamoto
IPC分类号: G06F15/16 , G06F9/38 , G06F15/173
CPC分类号: G06F15/17306 , G06F9/3867
摘要: Each NIC performs an aggregation calculation of data output from each processor in a normal order including a head NIC located at a head position of a first pipeline connection, an intermediate NIC located at an intermediate position, and a tail NIC located at a tail position, and when the aggregation calculation in the tail NIC is completed, each NIC starts distribution of an obtained aggregation result, distributes the aggregation result in a reverse order including the tail NIC, the intermediate NIC, and the head NIC, and outputs the aggregation result to the processor of the communication interface.
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公开(公告)号:US20240045674A1
公开(公告)日:2024-02-08
申请号:US18254974
申请日:2020-12-10
发明人: Tsuyoshi Ito , Kenji Tanaka , Yuki Arikawa , Kazuhiko Terada , Tsutomu Takeya , Takeshi Sakamoto
IPC分类号: G06F9/30
CPC分类号: G06F9/3001 , G06F9/30123
摘要: A transfer processing device includes an arithmetic instruction number acquisition circuit, a buffer circuit, a transfer information acquisition circuit, and a software processing unit. The arithmetic instruction number acquisition circuit acquires a transfer instruction number corresponding to transfer information which is information related to the next transfer destination of an arithmetic instruction. The buffer circuit is arranged between the arithmetic instruction number acquisition circuit and the transfer information acquisition circuit, and temporarily stores and relays the arithmetic instruction and the arithmetic instruction number supplied from the arithmetic instruction number acquisition circuit to the transfer information acquisition circuit. The transfer information acquisition circuit acquires transfer information on the basis of the arithmetic instruction number, and gives the acquired transfer information to the arithmetic instruction. The buffer circuit holds the arithmetic instruction number and the arithmetic instruction until an output request from the transfer information acquisition circuit is received.
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公开(公告)号:US20240007362A1
公开(公告)日:2024-01-04
申请号:US18253508
申请日:2020-11-30
发明人: Kenji Tanaka , Yuki Arikawa , Tsuyoshi Ito , Tsutomu Takeya , Takeshi Sakamoto
CPC分类号: H04L41/40 , H04L49/9068
摘要: In an NFV system, a protocol processor that receives a packet from an external network, a calculator that implements NFV for performing predetermined processing on the received packet, and an ANN calculator that performs processing using an ANN in the processing of the NFV are mounted on an NIC.
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公开(公告)号:US20230421510A1
公开(公告)日:2023-12-28
申请号:US18251325
申请日:2020-11-13
发明人: Yuki Arikawa , Kenji Tanaka , Tsuyoshi Ito , Tsutomu Takeya , Takeshi Sakamoto
IPC分类号: H04L49/20 , H04L49/253 , H04L43/062 , H04L43/0882
CPC分类号: H04L49/205 , H04L49/254 , H04L43/062 , H04L43/0882
摘要: A network card has a plurality of buffers each having different physical performances including a memory access speed or a storage capacity, and a buffer control circuit selects one buffer to be a packet storage destination from among the plurality of buffers on the basis of a priority or a service quality of a packet specified from header information of the packet received by a physical port and the physical performances of the plurality of buffers.
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