公开(公告)号：US20060077722A1

公开(公告)日：2006-04-13

申请号：US10962293

申请日：2004-10-08

申请人： Nicola Telecco ,  Vijaya Adusumilli

发明人： Nicola Telecco ,  Vijaya Adusumilli

IPC分类号： G11C7/10

CPC分类号： G11C29/1201 ,  G11C29/48 ,  G11C2029/1204 ,  G11C2029/5002

摘要： A direct memory access interface incorporates setting bit line selection data into a particular storage element of a desired page register element. The selection data and an access enable signal activate a memory access gate to electrically couple a memory access line with a desired memory bit line. Individual bit lines are selectable independently and more than one page register element may be selected at a time. Direct access of a memory bit line allows measurement and characterization operations to be carried out electrically with selected memory cells. This direct electrical access allows instrumentation to make voltage and current measurements necessary for characterization operations. Area that would otherwise be incorporated for an address decoder gate at each bit line selector circuit is saved since no on-chip decoding scheme is necessary. Additional area savings are realized since selection data storage are within a bidirectional storage element already present in a page register element.

摘要翻译： 直接存储器访问接口将设置位线选择数据合并到期望页寄存器元件的特定存储元件中。 选择数据和访问使能信号激活存储器访问门以将存储器访问线与期望的存储器位线电耦合。 单独的位线可独立选择，并且可以一次选择多于一个的页寄存器元件。 存储器位线的直接访问允许测量和表征操作与选择的存储单元电气执行。 这种直接电气访问允许仪器进行表征操作所需的电压和电流测量。 因为不需要片上解码方案，否则将在每个位线选择器电路处为地址解码器门并入的区域被保存。 由于选择数据存储在已经存在于页寄存器元件中的双向存储元件内，所以实现了额外的面积节省。

公开(公告)号：US20050289314A1

公开(公告)日：2005-12-29

申请号：US10875652

申请日：2004-06-23

申请人： Vijaya Adusumilli ,  Nicola Telecco ,  Abbas Tehrani

发明人： Vijaya Adusumilli ,  Nicola Telecco ,  Abbas Tehrani

IPC分类号： G06F12/00

CPC分类号： G11C16/26 ,  G06F11/1068 ,  G06F12/0804 ,  G06F12/0859 ,  G06F2212/2022 ,  G11C16/102

摘要： A system and method for performing a simultaneous external read operation during internal programming of a memory device is described. The memory device is configured to store data randomly and includes a source location, a destination location, a data register, and a cache register. The data register is configured to simultaneously write data to the destination and to the cache register. The system further includes a processing device (e.g., a microprocessor or microcontroller) for verifying an accuracy of any data received through electrical communication with the memory device. The processing device is additionally configured to provide for error correction if the received data is inaccurate, add random data to the data, if required, and then transfer the error-corrected and/or random data modified data back to the destination location.

摘要翻译： 描述用于在存储器件的内部编程期间执行同时外部读取操作的系统和方法。 存储器设备被配置为随机存储数据，并且包括源位置，目的地位置，数据寄存器和高速缓存寄存器。 数据寄存器被配置为同时将数据写入目的地和高速缓存寄存器。 该系统还包括处理装置（例如微处理器或微控制器），用于验证通过与存储装置的电气通信接收的任何数据的准确性。 如果接收到的数据不准确，则处理设备另外被配置为提供纠错，如果需要，则向数据添加随机数据，然后将纠错和/或随机的数据修改数据传送回目的地位置。

公开(公告)号：US07317630B2

公开(公告)日：2008-01-08

申请号：US11182374

申请日：2005-07-15

申请人： Nicola Telecco ,  Vijay P. Adusumilli ,  Anil Gupta ,  Edward Hui ,  Steven J. Schumann

发明人： Nicola Telecco ,  Vijay P. Adusumilli ,  Anil Gupta ,  Edward Hui ,  Steven J. Schumann

IPC分类号： G11C5/06

CPC分类号： G11C7/10 ,  H01L2224/05553 ,  H01L2224/48137 ,  H01L2224/49175

摘要： A nonvolatile memory apparatus includes a separate controller circuit and memory circuit. The controller circuit is fabricated on a first integrated circuit chip. The controller circuit includes a plurality of charge pump circuits, a system interface logic circuit, a memory control logic circuit, and one or more analog circuits. The memory circuit is fabricated on a second integrated circuit chip and includes a column decoder, a row decoder, a control register, and a data register. A memory-controller interface area includes a first plurality of die bond pads on the first integrated circuit chip and a second plurality of die bond pads on the second integrated circuit chip such that the first and second integrated circuit chips may be die-bonded together. A single controller circuit may interface with a plurality of memory circuits, thus further reducing overall costs as each memory circuit does not require a dedicated controller circuit.

摘要翻译： 非易失性存储装置包括单独的控制器电路和存储器电路。 控制器电路制造在第一集成电路芯片上。 控制器电路包括多个电荷泵电路，系统接口逻辑电路，存储器控制逻辑电路和一个或多个模拟电路。 存储器电路制造在第二集成电路芯片上，并且包括列解码器，行解码器，控制寄存器和数据寄存器。 存储器控制器接口区域包括第一集成电路芯片上的第一多个管芯接合焊盘和第二集成电路芯片上的第二多个管芯接合焊盘，使得第一和第二集成电路芯片可以芯片结合在一起。 单个控制器电路可以与多个存储器电路接口，从而进一步降低总体成本，因为每个存储器电路不需要专用控制器电路。

公开(公告)号：US07180276B2

公开(公告)日：2007-02-20

申请号：US11402730

申请日：2006-04-12

申请人： Nicola Telecco

发明人： Nicola Telecco

IPC分类号： G05F1/577

CPC分类号： G05F1/465

摘要： A voltage regulator for supplying two types of loads on a common chip, namely a high current load and a low current load. The voltage regulator employs a feedback loop to supply the low current load with a fine degree of regulation and a feed forward arrangement to supply the high current load with a coarse degree of regulation. The feedback loop employs a bandgap reference source feeding a comparator, with an output driver transistor drawing current from a common supply and having an output electrode connected to a voltage divider, allowing a sample of the output to be fed back to the comparator to maintain the desired output voltage. The output electrode also feeds a control transistor for the feed forward arrangement that also draws current from the common supply and supplies the high current load directly. An example of a single chip circuit employing the present invention is a charge pump where the high current load is a series of large capacitors used to multiply charge to produce a high voltage and the low current load is a plurality of clock circuits that apply timing pulses to switches for proper phasing of the capacitors and associated switches to achieve the desired high voltage.

摘要翻译： 用于在公共芯片上提供两种类型负载的电压调节器，即高电流负载和低电流负载。 电压调节器采用反馈回路来为低电流负载提供精细的调节程度和前馈布置，以提供粗调节的高电流负载。 反馈回路采用馈送比较器的带隙参考源，输出驱动晶体管从公共电源抽取电流，并且具有连接到分压器的输出电极，允许将输出的采样反馈到比较器以保持 所需输出电压。 输出电极还馈送用于前馈布置的控制晶体管，其也从公共电源吸取电流并直接提供高电流负载。 采用本发明的单芯片电路的例子是电荷泵，其中高电流负载是用于乘以电荷以产生高电压的一系列大电容器，并且低电流负载是施加定时脉冲的多个时钟电路 以切换电容器和相关开关的适当定相以实现期望的高电压。

公开(公告)号：US5673221A

公开(公告)日：1997-09-30

申请号：US592939

申请日：1996-01-29

申请人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

发明人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C16/02 ,  G11C17/00

CPC分类号： G11C11/5621 ,  G11C11/5642 ,  G11C2211/5632

摘要： A sensing circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2.sup.n (n>=2) different programming levels, comprises biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of the programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator. The variable reference current generator comprises an offset current generator permanently coupled to the current comparator, and m-2 distinct current generators, independently activatable by the successive approximation register, each one generating a current equal to a respective one of the plurality of cell current values.

摘要翻译： 用于在多个m = 2n（n> = 2）不同编程级别中可以采用一个编程级的多级存储器单元的串行二分感测的感测电路包括偏置装置，用于以预定的方式偏置待感测的存储器单元 条件，使得存储器单元以属于多个m个不同的单元电流值的值吸收单元电流，每个单元电流值对应于一个编程电平，用于将单元电流与产生的参考电流进行比较的电流比较器 通过可变参考电流发生器和逐次逼近寄存器来提供电流比较器的输出信号并控制可变参考电流发生器。 可变参考电流发生器包括永久地耦合到电流比较器的偏移电流发生器和由逐次逼近寄存器独立激活的m-2个不同的电流发生器，每个电流发生器产生等于多个电池电流值中的相应一个的电流 。

公开(公告)号：US07633800B2

公开(公告)日：2009-12-15

申请号：US11835572

申请日：2007-08-08

申请人： Vijay P. Adusumilli ,  Nicola Telecco

发明人： Vijay P. Adusumilli ,  Nicola Telecco

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C7/00

CPC分类号： G11C29/846

摘要： Column redundancy is provided outside of a FLASH memory chip using a separate companion controller chip. The companion chip initially receives and stores fuse address information from the FLASH memory chip for defective memory cells in the FLASH memory. In a read mode of operation, the companion control chip detects receipt of a defective address from the FLASH memory and stores in a redundant shift register redundant data that is downloaded from the FLASH memory chip. The redundant data is used to provide correct FLASH memory data to an external user that interfaces with the companion control chip. In a program mode of operation, the companion control chip provides redundant bits that are stored in redundant columns in the FLASH memory chip. The companion control chip provides flexibility by readily providing a number of different redundancy schemes for bits, nibbles, or bytes without requiring additional logic circuits in the FLASH memory chip itself. Data is transferred between the FLASH memory chip and the companion control chip a byte at a time.

摘要翻译： 使用单独的伴随控制器芯片在闪存芯片的外部提供列冗余。 伴随芯片最初接收并存储来自FLASH存储器芯片的熔丝地址信息用于闪速存储器中的有缺陷的存储单元。 在读取操作模式中，伴随控制芯片检测从FLASH存储器接收到缺陷地址，并存储在从闪速存储器芯片下载的冗余移位寄存器冗余数据中。 冗余数据用于向与配套控制芯片接口的外部用户提供正确的FLASH存储器数据。 在程序操作模式中，伴随控制芯片提供存储在闪速存储器芯片中的冗余列中的冗余位。 伴随的控制芯片通过容易地为位，半字节或字节提供多种不同的冗余方案来提供灵活性，而不需要FLASH存储器芯片本身中的附加逻辑电路。 数据在闪存存储器芯片和伴随控制芯片之间一个字节一次传输。

公开(公告)号：US07180779B2

公开(公告)日：2007-02-20

申请号：US11178965

申请日：2005-07-11

申请人： Nicola Telecco ,  Victor Nguyen

发明人： Nicola Telecco ,  Victor Nguyen

IPC分类号： G11C11/34

CPC分类号： G11C16/3468 ,  G11C16/26 ,  G11C16/3477

摘要： The present invention is related to semiconductor memories, and in particular, to a nonvolatile or flash memory and method that reduces the effect of or is tolerant of over-erased memory cells. When a memory cell is read, a read voltage is applied to at least one target memory cell, and a negative bias voltage that is lower than a threshold voltage of an over-erased memory cell is also applied to at least one other selected memory cell that is in the same row as the target memory cell. Applying a negative bias voltage to adjacent or proximate memory cells shuts off nearby cells to isolate current that may come from over-erased memory cells during a read, program, or erase operation.

摘要翻译： 本发明涉及半导体存储器，特别涉及一种减少过度擦除的存储单元的影响或容忍的非易失性或闪速存储器和方法。 当存储单元被读取时，读取电压被施加到至少一个目标存储单元，并且低于过擦除存储单元的阈值电压的负偏置电压也被施加到至少一个其他选择的存储单元 它与目标存储单元处于同一行。 对相邻或邻近的存储器单元施加负偏置电压会关闭附近的单元，以隔离在读取，编程或擦除操作期间来自过擦除的存储单元的电流。

公开(公告)号：US07159069B2

公开(公告)日：2007-01-02

申请号：US10875652

申请日：2004-06-23

申请人： Vijaya P. Adusumilli ,  Nicola Telecco ,  Abbas S. Tehrani

发明人： Vijaya P. Adusumilli ,  Nicola Telecco ,  Abbas S. Tehrani

IPC分类号： G06F12/16 ,  G11C29/00 ,  G11C7/10

CPC分类号： G11C16/26 ,  G06F11/1068 ,  G06F12/0804 ,  G06F12/0859 ,  G06F2212/2022 ,  G11C16/102

摘要： A system and method for performing a simultaneous external read operation during internal programming of a memory device is described. The memory device is configured to store data randomly and includes a source location, a destination location, a data register, and a cache register. The data register is configured to simultaneously write data to the destination and to the cache register. The system further includes a processing device (e.g., a microprocessor or microcontroller) for verifying an accuracy of any data received through electrical communication with the memory device. The processing device is additionally configured to provide for error correction if the received data is inaccurate, add random data to the data, if required, and then transfer the error-corrected and/or random data modified data back to the destination location.

摘要翻译： 描述用于在存储器件的内部编程期间执行同时外部读取操作的系统和方法。 存储器设备被配置为随机存储数据，并且包括源位置，目的地位置，数据寄存器和高速缓存寄存器。 数据寄存器被配置为同时将数据写入目的地和高速缓存寄存器。 该系统还包括处理装置（例如微处理器或微控制器），用于验证通过与存储装置的电气通信接收的任何数据的准确性。 如果接收到的数据不准确，则处理设备另外被配置为提供纠错，如果需要，则向数据添加随机数据，然后将纠错和/或随机的数据修改数据传送回目的地位置。

公开(公告)号：US06700415B2

公开(公告)日：2004-03-02

申请号：US10267339

申请日：2002-10-09

申请人： Nicola Telecco

发明人： Nicola Telecco

IPC分类号： G01K1500

CPC分类号： G11C7/067 ,  G11C7/065 ,  G11C7/08 ,  G11C2207/065

摘要： A sense amplifier that is configurable to operate in two modes in order to control a voltage swing on the sense amplifier output. The sense amplifier has two feedback paths including a first feedback path having a transistor with a fast response time in order to allow the circuit to operate as fast as possible, and a second feedback path for providing voltage swing control. In the first operating mode, the “turbo” mode, both feedback paths are in operation to provide a higher margin of swing control, thus higher sensing speed. In the second operating mode, the “non-turbo” mode, only the first feedback path is in operation which allows for greater stability and a reduction in power consumption.

摘要翻译： 读出放大器可配置为在两种模式下工作，以控制读出放大器输出上的电压摆幅。 读出放大器具有包括具有快速响应时间的晶体管的第一反馈路径的两个反馈路径，以便允许电路尽可能快地工作，以及用于提供电压摆幅控制的第二反馈路径。 在第一操作模式中，“涡轮”模式，两个反馈路径都在运行，以提供更高的摆幅控制余量，从而提高感测速度。 在第二操作模式中，“非涡轮”模式，只有第一反馈路径在运行中，这允许更大的稳定性和功耗的降低。

公开(公告)号：US5838612A

公开(公告)日：1998-11-17

申请号：US869072

申请日：1997-06-04

申请人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

发明人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C2211/5631

摘要： Reading circuit for multilevel non-volatile memory cell devices having, for each cell to be read, a selection line with which is associated a load and a decoupling and control stage with a feedback loop which stabilizes the voltage on a circuit node of the selection line. To this node are connected a current replica circuit which are controlled by the feedback loop. These include loads and circuit elements homologous to those associated with the selection line of the memory cell and have an output interface circuit for connection to current comparator circuit.

摘要翻译： 用于多电平非易失性存储单元器件的读取电路，对于要读取的每个单元，具有与负载和去耦合和控制级相关联的选择线，其具有稳定选择线的电路节点上的电压的反馈环路 。 对该节点连接由反馈回路控制的当前复制电路。 这些包括与与存储器单元的选择线相关的负载和电路元件同源的负载和电路元件，并且具有用于连接到电流比较器电路的输出接口电路。