公开(公告)号：US20170293265A1

公开(公告)日：2017-10-12

申请号：US15477237

申请日：2017-04-03

申请人： NXP USA, INC.

发明人： Didier Salle ,  Olivier Doare ,  Cristian Pavao Moreira ,  Birama Goumballa

IPC分类号： G04F10/00 ,  H03M1/10

CPC分类号： G04F10/005 ,  H03M1/1009

摘要： Various embodiments include a time to digital converter device comprising: a medium resolution delay unit including a plurality of buffers, the medium resolution delay unit configured to receive as inputs a reference clock signal and a data clock signal and configured to output a plurality of delayed data clock signals wherein the delay between the plurality of delayed data clock signal is a medium resolution delay value; a fine resolution delay unit including a plurality of cores configured to receive as inputs the reference clock signal and the plurality of delayed data clock signals from the medium resolution delay unit, wherein the plurality of cores includes: a first bank of delays configured to receive one of the plurality of the delayed data clock signals, a second bank of delays configured to receive the reference clock signal, and; and a fast flip flop connected to the outputs of the first bank of delays and the second bank of delays, wherein the output of the fast flip flop is used to check the phase alignment.

公开(公告)号：US09897975B2

公开(公告)日：2018-02-20

申请号：US15477237

申请日：2017-04-03

申请人： NXP USA, INC.

发明人： Didier Salle ,  Olivier Doare ,  Cristian Pavao Moreira ,  Birama Goumballa

IPC分类号： H03M1/10 ,  G04F10/00

CPC分类号： G04F10/005 ,  H03M1/1009

摘要： Various embodiments include a time to digital converter device comprising: a medium resolution delay unit including a plurality of buffers, the medium resolution delay unit configured to receive as inputs a reference clock signal and a data clock signal and configured to output a plurality of delayed data clock signals wherein the delay between the plurality of delayed data clock signal is a medium resolution delay value; a fine resolution delay unit including a plurality of cores configured to receive as inputs the reference clock signal and the plurality of delayed data clock signals from the medium resolution delay unit, wherein the plurality of cores includes: a first bank of delays configured to receive one of the plurality of the delayed data clock signals, a second bank of delays configured to receive the reference clock signal, and; and a fast flip flop connected to the outputs of the first bank of delays and the second bank of delays, wherein the output of the fast flip flop is used to check the phase alignment.

公开(公告)号：US10648870B2

公开(公告)日：2020-05-12

申请号：US15464145

申请日：2017-03-20

申请人： NXP USA, Inc.

发明人： Birama Goumballa ,  Didier Salle ,  Olivier Doare ,  Cristian Pavao Moreira

IPC分类号： G01K15/00 ,  G01K7/01 ,  G01K7/16 ,  G05F3/26

摘要： Disclosed is a temperature sensor including a first current generator configured to generate a proportional to absolute temperature (PTAT) current, a second current generator configured to generate an inverse PTAT (IPTAT) current, the PTAT current and IPTAT current being combined to form a reference current having a sensitivity relative to temperature, a plurality of current mirrors to adjust the sensitivity and gain of the reference current, and a variable resistor to set an output calibration voltage based on the generated current.