公开(公告)号：US20250015814A1

公开(公告)日：2025-01-09

申请号：US18218366

申请日：2023-07-05

Applicant: NXP B.V.

Inventor： Maarten Jelmar MOLENDIJK ,  Robert van VELDHOVEN

IPC: H03M3/00

Abstract: A device may include a sigma-delta analog-to-digital converter (ADC) configured to convert an analog input signal to a digital signal that is a digital approximation of the analog input signal. A bitstream modifier is configured to receive the digital signal, output a first signal that is based on the digital signal at a first output terminal and output a first difference signal at a second output terminal that includes a first difference value between a first value of the digital signal and a second value of the digital signal. The second value is immediately prior to the first value in the digital signal. An error correction system is configured to receive the first signal, receive the first difference signal, use the first signal and the first difference signal to determine a correction value, and modify the digital signal to generate a corrected digital signal by applying the correction value.

公开(公告)号：US20250007532A1

公开(公告)日：2025-01-02

申请号：US18215003

申请日：2023-06-27

Applicant: NXP B.V.

Inventor： Robert van VELDHOVEN ,  Maarten Jelmar MOLENDIJK

IPC: H03M3/00

Abstract: A device may include an input terminal configured to receive an analog input signal. A device may include an output terminal configured to output a digital signal x, wherein the digital signal x includes a digital approximation of the analog input signal. A device may include an error correction system connected to the ADC, the error correction system including a first input terminal configured to receive an Nth powered version of the digital signal x, wherein N is a whole number equal to or greater than two, wherein the error correction system is configured to: use the Nth powered version of the digital signal x to determine a correction value; and modify the digital signal x to generate a corrected digital signal by applying the correction value to compensate for analog-to-digital conversion errors occurring within the ADC.