公开(公告)号：US12267153B2

公开(公告)日：2025-04-01

申请号：US17660222

申请日：2022-04-22

Applicant: NXP B.V.

Inventor： Mark Andrew Schellhorn ,  Bernard Francois St-Denis ,  John Pillar

IPC: G06F13/28 ,  H04J3/06

Abstract: A network station scheduling a frame to be transmitted by a transmitter of the network station at a transmit time. The transmit time is based on a first clock. A request is then issued to a direct memory access (DMA) circuit to retrieve the frame from a system memory. An advance time offset associated with the first clock is determined based on an estimated DMA latency of the DMA circuit. A frame retrieved by the DMA circuit is provided to a staging circuit. When a time of a second clock reaches the transmit time of the frame in the staging circuit, the frame is transmitted at the transmit time. In an example, a time of the first clock is ahead of a time of the second clock by the advance time offset.

公开(公告)号：US20230344539A1

公开(公告)日：2023-10-26

申请号：US17660222

申请日：2022-04-22

Applicant: NXP B.V.

Inventor： Mark Andrew Schellhorn ,  Bernard Francois St-Denis ,  John Pillar

IPC: H04J3/06 ,  G06F13/28

CPC classification number: H04J3/0667 ,  H04J3/0697 ,  G06F13/287

Abstract: A network station scheduling a frame to be transmitted by a transmitter of the network station at a transmit time. The transmit time is based on a first clock. A request is then issued to a direct memory access (DMA) circuit to retrieve the frame from a system memory. An advance time offset associated with the first clock is determined based on an estimated DMA latency of the DMA circuit. A frame retrieved by the DMA circuit is provided to a staging circuit. When a time of a second clock reaches the transmit time of the frame in the staging circuit, the frame is transmitted at the transmit time. In an example, a time of the first clock is ahead of a time of the second clock by the advance time offset.