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    RFID DEVICE AND METHOD OF OPERATING AN RFID DEVICE
    2.
    发明申请
    RFID DEVICE AND METHOD OF OPERATING AN RFID DEVICE 有权

    公开(公告)号：US20210271832A1

    公开(公告)日：2021-09-02

    申请号：US17168246

    申请日：2021-02-05

    Applicant: NXP B.V.

    Inventor： Martin FELDHOFER ,  Franz Amtmann ,  Peter Thüringer

    IPC: G06K7/10 ,  G06K19/07

    Abstract: In accordance with a first aspect of the present disclosure, a radio frequency identification (RFID) device is provided, comprising a first power domain, a second power domain, a first processing unit, and a second processing unit, wherein the first processing unit is configured to execute one or more first operations and the second processing unit is configured to execute one or more second operations, wherein the first operations output intermediate data which are used as input for the second operations, and wherein the first processing unit is configured to operate in the first power domain and the second processing unit is configured to operate in the second power domain, said first power domain having a larger amount of available power than the second power domain. In accordance with further aspects of the present disclosure, a corresponding method of operating a radio frequency identification (RFID) device is conceived, and a corresponding computer program is provided.

    DATA CARRIER PROVIDED WITH AT LEAST TWO DECODING STAGES
    3.
    发明申请
    DATA CARRIER PROVIDED WITH AT LEAST TWO DECODING STAGES 审中-公开
    数据载体提供至少两个解码阶段

    公开(公告)号：US20150110226A1

    公开(公告)日：2015-04-23

    申请号：US14574690

    申请日：2014-12-18

    Applicant: NXP B.V.

    Inventor： Franz Amtmann ,  Dominik Josef Berger ,  Wolfgang Eber ,  Stefan Posch ,  Robert Rechberger

    IPC: G06K19/07

    CPC classification number: G06K19/0723 ,  G06K19/073

    Abstract: A data carrier device is disclosed. The data carrier device includes a demodulation device configured to demodulate a received modulated carrier signal and output the included encoded data signal and a decoding device configured to decode the encoded data signal and output data. The decoding device includes a first decoding stage and a second decoding stage, wherein the first decoding stage is configured to decode said data signal in conformity with a first method and the second decoding stage is configured to decode said data signal in conformity with a second method, wherein the first method is Manchester and the second method is Miller.

    Abstract translation: 公开了一种数据载体装置。 数据载体装置包括：解调装置，被配置为解调接收到的调制载波信号并输出​​所包括的编码数据信号;以及解码装置，被配置为对编码数据信号进行解码并输出数据。 解码装置包括第一解码级和第二解码级，其中第一解码级被配置为根据第一方法对所述数据信号进行解码，并且第二解码级被配置为根据第二方法对所述数据信号进行解码 ，其中第一种方法是曼彻斯特，第二种方法是米勒。

    ELECTRONIC COUNTER IN NON-VOLATILE LIMITED ENDURANCE MEMORY
    4.
    发明申请
    ELECTRONIC COUNTER IN NON-VOLATILE LIMITED ENDURANCE MEMORY 有权
    非易失性存储器中的电子计数器

    公开(公告)号：US20140089612A1

    公开(公告)日：2014-03-27

    申请号：US14029659

    申请日：2013-09-17

    Applicant: NXP B.V.

    Inventor： Martin Feldhofer ,  Franz Amtmann ,  Soenke Ostertun ,  Alicia da Conceicao

    IPC: G06F12/00

    CPC classification number: G06F12/00 ,  H03K21/403

    Abstract: An electronic counter comprising a sequence of memory cells, each memory cell being non-volatile and supporting a one state and a zero state, the counter being configured to represent at least part of a current counting-state of the counter as a pattern of one and zero states in the memory cells of the sequence of memory cells, and increment logic configured to advance the pattern of one and zero states to a next pattern to represent an increment of the counter, the increment logic comprising programming increment logic and erasing increment logic, the increment logic being configured to alternate between a programming phase in which the programming increment logic advances the pattern, and an erasing phase in which the erasing increment logic advances the pattern, wherein the programming increment logic is configured to program a next cell of the sequence of non-volatile memory cells from a zero state to a one state, the program phase terminating when all memory cells of the sequence of memory cells are in the one state, the erasing increment logic is configured to erase a next cell of the sequence of non-volatile memory cells from a one state to a zero state, the erase phase terminating when all memory cells of the sequence of memory cells are in the zero state.

    Abstract translation: 一种包括存储器单元序列的电子计数器，每个存储单元是非易失性的并且支持一种状态和零状态，所述计数器被配置为将计数器的当前计数状态的至少一部分表示为一种模式 以及存储器单元序列的存储器单元中的零状态，以及被配置为将一个和零个状态的模式推进到下一个模式以表示计数器的增量的递增逻辑，该增量逻辑包括编程增量逻辑和擦除增量逻辑 所述增量逻辑被配置为在所述编程增量逻辑推进所述模式的编程阶段与所述擦除增量逻辑使所述模式前进的擦除阶段之间交替，其中所述编程增量逻辑被配置为对 非易失性存储单元的序列从零状态到一状态，程序阶段在序列的所有存储单元时终止 所述擦除增量逻辑被配置为将所述非易失性存储器单元序列的下一个单元从一个状态擦除到零状态，所述擦除阶段在所述存储器单元的序列的所有存储单元 存储单元处于零状态。

    ENERGY HARVESTING UNIT AND OPERATING METHOD THEREOF
    5.
    发明公开
    ENERGY HARVESTING UNIT AND OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20240154458A1

    公开(公告)日：2024-05-09

    申请号：US18503226

    申请日：2023-11-07

    Applicant: NXP B.V.

    Inventor： Peter Thuringer ,  Ulrich Andreas Muehlmann ,  Daniel Lopez-Diaz ,  Franz Amtmann ,  Yoganathan Sivakumar

    IPC: H02J50/00 ,  H02J50/20 ,  H02J50/40

    CPC classification number: H02J50/001 ,  H02J50/20 ,  H02J50/402

    Abstract: An energy harvesting unit includes a plurality of antennas configured to receive one or more signals and a plurality of first charge pumps, in which each of the first charge pumps is operatively coupled to one of the antennas, thereby forming pairs of antennas and first charge pumps. The energy harvesting unit also includes a selection unit configured to measure and compare output voltages of the first charge pumps and to select, from the antennas, a specific antenna. The specific antenna is coupled to the first charge pump that produces the highest output voltage. The energy harvesting unit also includes a multiplexer configured to couple the specific antenna selected by the selection unit to a second charge pump.

    INTEGRATED CIRCUIT AND MEASUREMENT METHOD
    7.
    发明申请
    INTEGRATED CIRCUIT AND MEASUREMENT METHOD 有权

    公开(公告)号：US20210063455A1

    公开(公告)日：2021-03-04

    申请号：US16944435

    申请日：2020-07-31

    Applicant: NXP B.V.

    Inventor： Rainer Stadlmair ,  Franz Amtmann

    IPC: G01R27/26 ,  G06K19/07

    Abstract: In accordance with a first aspect of the present disclosure, an integrated circuit is provided, comprising a current source and a reference capacitor, the integrated circuit being configured to: inject, using said current source, a first current in an external measurement capacitor and determine a first amount of time within which a resulting voltage on the measurement capacitor reaches a voltage threshold; inject, using said current source, a second current in the reference capacitor and determine a second amount of time within which a resulting voltage on the reference capacitor reaches said voltage threshold; detect a change of the capacitance on the measurement capacitor using a difference between the first amount of time and the second amount of time. In accordance with a second aspect of the present disclosure, a corresponding measurement method is conceived.

    Smart objects
    8.
    发明授权
    Smart objects 有权

    公开(公告)号：US10083386B2

    公开(公告)日：2018-09-25

    申请号：US15411955

    申请日：2017-01-20

    Applicant: NXP B.V.

    Inventor： Reinhard Meindl ,  Franz Amtmann

    IPC: G06K19/07 ,  H04B5/00

    CPC classification number: G06K19/0724 ,  G06K19/0723 ,  H04B5/0031 ,  H04B5/0037

    Abstract: An object is disclosed, the object (100) comprising a body comprising an antenna; and an integrated circuit embedded in the body and electrically connected to the antenna for receiving and transmitting wireless signals. The integrated circuit receives wireless signals at first and second different frequencies, waits until a command is received at the first frequency from a first reader device before transmitting a first signal and, upon detection of a signal at a second frequency different to the first frequency from a second reader device (201), transmits a second signal without waiting until a command is received.

    Integrated circuit and measurement method
    10.
    发明授权
    Integrated circuit and measurement method 有权

    公开(公告)号：US11500003B2

    公开(公告)日：2022-11-15

    申请号：US16944435

    申请日：2020-07-31

    Applicant: NXP B.V.

    Inventor： Rainer Stadlmair ,  Franz Amtmann

    IPC: G01R27/26 ,  G06K19/07

    Abstract: In accordance with a first aspect of the present disclosure, an integrated circuit is provided, comprising a current source and a reference capacitor, the integrated circuit being configured to: inject, using said current source, a first current in an external measurement capacitor and determine a first amount of time within which a resulting voltage on the measurement capacitor reaches a voltage threshold; inject, using said current source, a second current in the reference capacitor and determine a second amount of time within which a resulting voltage on the reference capacitor reaches said voltage threshold; detect a change of the capacitance on the measurement capacitor using a difference between the first amount of time and the second amount of time. In accordance with a second aspect of the present disclosure, a corresponding measurement method is conceived.

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