公开(公告)号：US20240036952A1

公开(公告)日：2024-02-01

申请号：US17955052

申请日：2022-09-28

Applicant: NVIDIA Corporation

Inventor： Ze Long ,  Kyrylo Perelygin ,  Harold Carter Edwards ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Jaydeep Marathe ,  Ronny Meir Krashinsky ,  Girish Bhaskarrao Bharambe

IPC: G06F9/54 ,  G06F9/48

CPC classification number: G06F9/544 ,  G06F9/4881

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to determine which of two or more blocks of threads are to be scheduled in parallel.

公开(公告)号：US20240036951A1

公开(公告)日：2024-02-01

申请号：US17955023

申请日：2022-09-28

Applicant: NVIDIA Corporation

Inventor： Ze Long ,  Kyrylo Perelygin ,  Harold Carter Edwards ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Jaydeep Marathe ,  Ronny Meir Krashinsky ,  Girish Bhaskarrao Bharambe

IPC: G06F9/54 ,  G06F9/48

CPC classification number: G06F9/544 ,  G06F9/4881

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate two or more blocks of threads to be scheduled in parallel.

公开(公告)号：US20240036954A1

公开(公告)日：2024-02-01

申请号：US17955106

申请日：2022-09-28

Applicant: NVIDIA Corporation

Inventor： Ze Long ,  Kyrylo Perelygin ,  Harold Carter Edwards ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Jaydeep Marathe ,  Ronny Meir Krashinsky ,  Girish Bhaskarrao Bharambe

IPC: G06F9/54 ,  G06F9/48

CPC classification number: G06F9/544 ,  G06F9/4881

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate one or more attributes of one or more groups of blocks of one or more threads.

公开(公告)号：US20240036917A1

公开(公告)日：2024-02-01

申请号：US17955110

申请日：2022-09-28

Applicant: NVIDIA Corporation

Inventor： Ze Long ,  Kyrylo Perelygin ,  Harold Carter Edwards ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Jaydeep Marathe ,  Ronny Meir Krashinsky ,  Girish Bhaskarrao Bharambe

IPC: G06F9/48 ,  G06F9/50 ,  G06F9/54

CPC classification number: G06F9/4881 ,  G06F9/5044 ,  G06F9/545

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate a maximum number of blocks of threads to be scheduled in parallel.

公开(公告)号：US11080111B1

公开(公告)日：2021-08-03

申请号：US16799462

申请日：2020-02-24

Applicant: NVIDIA Corporation

Inventor： Kyrylo Perelygin ,  Cory Perry ,  Ze Long

IPC: G06F9/54 ,  G06F9/445 ,  G06F9/48

Abstract: Apparatuses, systems, and techniques to execute programs in a single hardware context on a graphics processing unit (GPU). In at least one embodiment, resource management patches expressed in library or executable code are applied to one or more kernels to ensure execution in a shared context on a GPU.

公开(公告)号：US20240036956A1

公开(公告)日：2024-02-01

申请号：US17955163

申请日：2022-09-28

Applicant: NVIDIA Corporation

Inventor： Ze Long ,  Kyrylo Perelygin ,  Harold Carter Edwards ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Jaydeep Marathe ,  Ronny Meir Krashinsky ,  Girish Bhaskarrao Bharambe

IPC: G06F9/54 ,  G06F9/48 ,  G06F9/30

CPC classification number: G06F9/544 ,  G06F9/4881 ,  G06F9/30072

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate whether one or more threads within a group of blocks of threads have performed a barrier instruction and to cause performance of one or more threads within the group of blocks of threads to stop at least until all threads within the group of blocks have performed the barrier instruction.

公开(公告)号：US20240036953A1

公开(公告)日：2024-02-01

申请号：US17955085

申请日：2022-09-28

Applicant: NVIDIA Corporation

Inventor： Ze Long ,  Kyrylo Perelygin ,  Harold Carter Edwards ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Jaydeep Marathe ,  Ronny Meir Krashinsky ,  Girish Bhaskarrao Bharambe

IPC: G06F9/54 ,  G06F9/48

CPC classification number: G06F9/544 ,  G06F9/4881

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate a scheduling policy of one or more blocks of one or more threads.

公开(公告)号：US20240036918A1

公开(公告)日：2024-02-01

申请号：US17955123

申请日：2022-09-28

Applicant: NVIDIA Corporation

Inventor： Ze Long ,  Kyrylo Perelygin ,  Harold Carter Edwards ,  Gokul Ramaswamy Hirisave Chandra Shekhara ,  Jaydeep Marathe ,  Ronny Meir Krashinsky ,  Girish Bhaskarrao Bharambe

IPC: G06F9/48 ,  G06F9/54 ,  G06F8/41

CPC classification number: G06F9/4881 ,  G06F9/545 ,  G06F8/456

Abstract: Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to cause a kernel to be generated to cause two or more blocks of two or more threads to be scheduled in parallel.

公开(公告)号：US20230221960A1

公开(公告)日：2023-07-13

申请号：US17575563

申请日：2022-01-13

Applicant: NVIDIA Corporation

Inventor： Maciej Marcin Piechotka ,  Kyrylo Perelygin ,  Ze Long ,  Raphael Dominique Pierre Boissel ,  Michael Murphy ,  Anis Ladram ,  Isaac Gelado ,  Girish Bhaskarrao Bharambe ,  Sebastian Piotr Jodlowski

IPC: G06F9/38 ,  G06F9/54 ,  G06F13/16

CPC classification number: G06F9/3822 ,  G06F9/545 ,  G06F13/1663 ,  G06F9/3879

Abstract: Apparatuses, systems, and techniques to enable a program to access data regardless of where said data is stored. In at least one embodiment, a system enables a program to access data regardless of where said data is stored, based on, for example, one or more locations encoding one or more addresses of said data.

公开(公告)号：US12248788B2

公开(公告)日：2025-03-11

申请号：US17691690

申请日：2022-03-10

Applicant: NVIDIA Corporation

Inventor： Prakash Bangalore Prabhakar ,  Gentaro Hirota ,  Ronny Krashinsky ,  Ze Long ,  Brian Pharris ,  Rajballav Dash ,  Jeff Tuckey ,  Jerome F. Duluk, Jr. ,  Lacky Shah ,  Luke Durant ,  Jack Choquette ,  Eric Werness ,  Naman Govil ,  Manan Patel ,  Shayani Deb ,  Sandeep Navada ,  John Edmondson ,  Greg Palmer ,  Wish Gandhi ,  Ravi Manyam ,  Apoorv Parle ,  Olivier Giroux ,  Shirish Gadre ,  Steve Heinrich

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52 ,  G06F9/54 ,  G06F13/16 ,  G06T1/60

Abstract: Distributed shared memory (DSMEM) comprises blocks of memory that are distributed or scattered across a processor (such as a GPU). Threads executing on a processing core local to one memory block are able to access a memory block local to a different processing core. In one embodiment, shared access to these DSMEM allocations distributed across a collection of processing cores is implemented by communications between the processing cores. Such distributed shared memory provides very low latency memory access for processing cores located in proximity to the memory blocks, and also provides a way for more distant processing cores to also access the memory blocks in a manner and using interconnects that do not interfere with the processing cores' access to main or global memory such as hacked by an L2 cache. Such distributed shared memory supports cooperative parallelism and strong scaling across multiple processing cores by permitting data sharing and communications previously possible only within the same processing core.