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公开(公告)号:US20240342600A1
公开(公告)日:2024-10-17
申请号:US18529260
申请日:2023-12-05
Applicant: NVIDIA Corporation
Inventor: Sau Yan Keith LI , Ziad Ben Hadj Alouane , Seth Schneider , Viktor Grigoryevich Vandanov , Rouslan Lyubomirov Dimitrov
IPC: A63F13/52 , A63F13/355
CPC classification number: A63F13/52 , A63F13/355
Abstract: Disclosed are apparatuses, systems, and techniques that eliminate frame tears, reduce stutters, and minimize latency in frame rendering pipelines. The techniques include but are not limited to collecting one or more latency metrics associated with rendering of a first set of one or more frames using a graphics rendering pipeline operating according to a first frame-generation schedule. The techniques further include modifying, using the one or more latency metrics, a first frame-generation schedule to obtain a second frame-generation schedule. The techniques include, rendering using the graphics rendering pipeline operating according to the second frame-generation schedule, a second set of one or more frames, and causing the second set of frames to be displayed on a display device.
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公开(公告)号:US20240286043A1
公开(公告)日:2024-08-29
申请号:US18174163
申请日:2023-02-24
Applicant: NVIDIA Corporation
Inventor: Lucien Dunning , Seth Schneider , Dwayne Swoboda , Marko Mitic , Daniel Rohrer
Abstract: In examples, properties of an execution environment may be verified for a game session to comply with security policies based at least on analyzing attestation reports generated using one or more host devices. Content items may be associated with the game session to indicate the verification for presentation with a live stream video of the game session, in a pre-recorded video of the game session, and/or in another user interface associated with the game session. A record of the verification may be stored in a database, and the database may be queried to display the content item and/or to determine whether the verification occurred. The attestation reports may include an attestation report(s) generated using an input device(s) used to capture user inputs for the game session, such as an input device used to control the game session and/or provide a video capture of the player during the game session.
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公开(公告)号:US20250150371A1
公开(公告)日:2025-05-08
申请号:US19016364
申请日:2025-01-10
Applicant: NVIDIA Corporation
Inventor: David Lim , Hsien-Li Lin , Tom Jozef Denis Verbeure , Gerrit Slavenburg , Seth Schneider
IPC: H04L43/0852 , G06F3/14 , H04L43/065 , H04L43/106
Abstract: In various examples, latency of human interface devices (HIDs) may be accounted for in determining an end-to-end latency of a system. For example, when an input is received at an HID, an amount of time for the input to reach a connected device may be computed by the HID and included in a data packet transmitted by the HID device to the connected device. The addition of the peripheral latency to the end-to-end latency determination may provide a more comprehensive latency result for the system and, where the peripheral latency of an HID is determined to have a non-negligible contribution to the end-to-end latency, a new HID component may be implemented, a configuration setting associated with the HID component may be updated, and/or other actions may be taken to reduce the contribution of the peripheral latency to the overall latency of the system.
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公开(公告)号:US20240202860A1
公开(公告)日:2024-06-20
申请号:US18594099
申请日:2024-03-04
Applicant: NVIDIA Corporation
Inventor: Sau Yan Keith Li , Seth Schneider , Cody Robson , Lars Nordskog , Charles Hansen , Rouslan Dimitrov
CPC classification number: G06T1/20 , G06F9/3836 , G06F9/4881
Abstract: A weighted average execution time associated with each execution stage of a plurality of execution stages used to process a plurality of frames in parallel is obtained. The processing of each of the plurality of frames is performed at each of the plurality of execution stages in a sequential order, starting with an initial execution stage and continuing with each subsequent execution stage. A first largest weighted average execution time associated with one of the plurality of execution stages is determined. A delay to the initial execution stage prior to processing a first next frame is applied. The delay is determined based on the first largest weighted average execution time.
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公开(公告)号:US20220180173A1
公开(公告)日:2022-06-09
申请号:US17114144
申请日:2020-12-07
Applicant: NVIDIA Corporation
Inventor: Aditya Jonnalagadda , Iuri Frosio , Joohwan Kim , Seth Schneider
Abstract: Apparatuses, systems, and techniques to detect cheating in a computer game. In at least one embodiment, one or more circuits use one or more neural networks to detect cheating by one or more users of a computer game based, at least in part, on one or more images generated by the computer game.
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公开(公告)号:US20220109617A1
公开(公告)日:2022-04-07
申请号:US17064452
申请日:2020-10-06
Applicant: NVIDIA Corporation
Inventor: David Lim , Hsien-Li Lin , Tom Jozef Denis Verbeure , Gerrit Slavenburg , Seth Schneider
IPC: H04L12/26
Abstract: In various examples, latency of human interface devices (HIDs) may be accounted for in determining an end-to-end latency of a system. For example, when an input is received at an HID, an amount of time for the input to reach a connected device may be computed by the HID and included in a data packet transmitted by the HID device to the connected device. The addition of the peripheral latency to the end-to-end latency determination may provide a more comprehensive latency result for the system and, where the peripheral latency of an HID is determined to have a non-negligible contribution to the end-to-end latency, a new HID component may be implemented, a configuration setting associated with the HID component may be updated, and/or other actions may be taken to reduce the contribution of the peripheral latency to the overall latency of the system.
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公开(公告)号:US20250104670A1
公开(公告)日:2025-03-27
申请号:US18373748
申请日:2023-09-27
Applicant: NVIDIA Corporation
IPC: G09G5/395
Abstract: Disclosed are apparatuses, systems, and techniques that reduce latency of frame processing pipelines. The techniques include but are not limited to causing a display to set a refresh rate that matches a frame rendering rate of an application and rendering, with the frame rendering rate, a plurality of frames. Rendering frames includes generating, using a first processing unit, sets of instructions associated with respective frames and generated starting at times spaced with the refresh rate, processing, using a second processing unit, the sets of instructions to render the frames, and causing the display to display the rendered frames.
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公开(公告)号:US12212480B2
公开(公告)日:2025-01-28
申请号:US17064452
申请日:2020-10-06
Applicant: NVIDIA Corporation
Inventor: David Lim , Hsien-Li Lin , Tom Jozef Denis Verbeure , Gerrit Slavenburg , Seth Schneider
IPC: H04L43/08 , G06F3/14 , H04L43/065 , H04L43/0852 , H04L43/106
Abstract: In various examples, latency of human interface devices (HIDs) may be accounted for in determining an end-to-end latency of a system. For example, when an input is received at an HID, an amount of time for the input to reach a connected device may be computed by the HID and included in a data packet transmitted by the HID device to the connected device. The addition of the peripheral latency to the end-to-end latency determination may provide a more comprehensive latency result for the system and, where the peripheral latency of an HID is determined to have a non-negligible contribution to the end-to-end latency, a new HID component may be implemented, a configuration setting associated with the HID component may be updated, and/or other actions may be taken to reduce the contribution of the peripheral latency to the overall latency of the system.
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公开(公告)号:US20240232360A1
公开(公告)日:2024-07-11
申请号:US18151175
申请日:2023-01-06
Applicant: NVIDIA Corporation
Inventor: Lucien Dunning , Seth Schneider , Dwayne Swoboda , Marko Mitic , Adam Zabrocki
Abstract: In examples, a VM may receive and aggregate a first attestation report corresponding to a
CPU and a second attestation report corresponding to a GPU. The aggregated data may be provided to an attestation service, which may verify the attestation reports indicate a TCB is to include the VM and GPU state data and is to isolate the GPU state data and the VM from an untrusted host OS. Based at least on the TCB being verified, the VM may perform one or more operations using the TCB. The TCB may include a trusted hypervisor to isolate the VM and GPU state data within the GPU(s) from the untrusted host OS. The trusted hypervisor may prevent the host OS from accessing device memory assigned to the VM based at least on controlling an IOMMU and/or second-level address translation (SLAT) used to access the data.-
公开(公告)号:US11922533B2
公开(公告)日:2024-03-05
申请号:US17448258
申请日:2021-09-21
Applicant: NVIDIA Corporation
Inventor: Sau Yan Keith Li , Seth Schneider , Cody Robson , Lars Nordskog , Charles Hansen , Rouslan Dimitrov
CPC classification number: G06T1/20 , G06F9/3836 , G06F9/4881
Abstract: A weighted average execution time associated with each execution stage of a plurality of execution stages used to process a plurality of frames in parallel is obtained. The processing of each of the plurality of frames is performed at each of the plurality of execution stages in a sequential order, starting with an initial execution stage and continuing with each subsequent execution stage. A first largest weighted average execution time associated with one of the plurality of execution stages is determined. A delay to the initial execution stage prior to processing a first next frame is applied. The delay is determined based on the first largest weighted average execution time.
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