公开(公告)号：US20210193602A1

公开(公告)日：2021-06-24

申请号：US17121804

申请日：2020-12-15

Applicant: Nepes CO., LTD.

Inventor： Jun Kyu LEE ,  Su Yun Kim ,  Dong Hoon OH ,  Yong Tae KWON ,  Ju Hyun NAM

IPC: H01L23/00

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a lower structure including a semiconductor chip having a chip terminal; an external connection terminal connecting the semiconductor chip to an external device, and an intermediate connection structure including an upper surface and a lower surface opposite to the upper surface, and positioned between the lower structure and the external connection terminal.

公开(公告)号：US20220278053A1

公开(公告)日：2022-09-01

申请号：US17442796

申请日：2020-03-24

Applicant: NEPES CO., LTD.

Inventor： Ju Hyun NAM ,  Jun Kyu LEE ,  Yong Tae KWON ,  Su Yun KIM ,  Dong Hoon OH

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48

Abstract: A technical idea of the present disclosure provides a semiconductor package, as a semiconductor package mounted on a circuit board, including: a body portion including a semiconductor chip, and a first surface and a second surface opposite to each other; and a structure including n insulating layers stacked on at least one of the first surface and the second surface of the body portion, wherein the semiconductor package has a predetermined target coefficient of thermal expansion (CTE), and the n insulating layers and the body portion have a thickness and a CTE satisfying a condition that an effective CTE of the semiconductor package becomes equal to the predetermined target CTE.