公开(公告)号：US07652942B2

公开(公告)日：2010-01-26

申请号：US11757099

申请日：2007-06-01

申请人： Myeong-o Kim ,  Yun-sang Lee

发明人： Myeong-o Kim ,  Yun-sang Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/14 ,  G11C7/06 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2207/005

摘要： A sense amplifier includes a reference signal providing unit and an internal sense amplification unit. The reference signal providing unit provides a reference bit line signal in response to a reference control signal. The internal sense amplification unit receives the reference bit line signal and data signals that correspond to the data. The received signals are provided through bit lines connected to the memory cell array. The internal sense amplification unit senses the received reference bit line signal and the data signals and amplifies the sensed signals. The sense amplifier senses data stored in memory cells connected to dummy bit lines of the outmost memory cell array of a semiconductor memory device such that the memory cells that are not used can be used. Accordingly, the design area and cost of the semiconductor memory device can be reduced.

摘要翻译： 读出放大器包括参考信号提供单元和内部检测放大单元。 参考信号提供单元响应于参考控制信号提供参考位线信号。 内部检测放大单元接收对应于数据的参考位线信号和数据信号。 接收的信号通过连接到存储单元阵列的位线来提供。 内部感测放大单元感测接收的参考位线信号和数据信号并放大所感测的信号。 感测放大器感测存储在连接到半导体存储器件的最外存储单元阵列的虚拟位线的存储器单元中的数据，使得可以使用未使用的存储器单元。 因此，可以减少半导体存储器件的设计面积和成本。

公开(公告)号：US20080056039A1

公开(公告)日：2008-03-06

申请号：US11757099

申请日：2007-06-01

申请人： Myeong-o Kim ,  Yun-sang Lee

发明人： Myeong-o Kim ,  Yun-sang Lee

IPC分类号： G11C7/06

CPC分类号： G11C7/14 ,  G11C7/06 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2207/005

摘要： A sense amplifier includes a reference signal providing unit and an internal sense amplification unit. The reference signal providing unit provides a reference bit line signal in response to a reference control signal. The internal sense amplification unit receives the reference bit line signal and data signals that correspond to the data. The received signals are provided through bit lines connected to the memory cell array. The internal sense amplification unit senses the received reference bit line signal and the data signals and amplifies the sensed signals. The sense amplifier senses data stored in memory cells connected to dummy bit lines of the outmost memory cell array of a semiconductor memory device such that the memory cells that are not used can be used. Accordingly, the design area and cost of the semiconductor memory device can be reduced.

摘要翻译： 读出放大器包括参考信号提供单元和内部检测放大单元。 参考信号提供单元响应于参考控制信号提供参考位线信号。 内部检测放大单元接收对应于数据的参考位线信号和数据信号。 接收的信号通过连接到存储单元阵列的位线来提供。 内部感测放大单元感测接收的参考位线信号和数据信号并放大所感测的信号。 感测放大器感测存储在连接到半导体存储器件的最外存储单元阵列的虚拟位线的存储器单元中的数据，使得可以使用未使用的存储器单元。 因此，可以减少半导体存储器件的设计面积和成本。

公开(公告)号：US06879533B2

公开(公告)日：2005-04-12

申请号：US10609071

申请日：2003-06-27

申请人： Moo-sung Chae ,  Myeong-o Kim ,  Sung-min Seo

发明人： Moo-sung Chae ,  Myeong-o Kim ,  Sung-min Seo

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1069 ,  G11C7/1048 ,  G11C7/1051

摘要： An integrated circuit memory device can include a memory cell array having a plurality of memory cells, and a bit line sense amplifier configured to amplify data on a pair of bit lines from a memory cell of the memory cell array and to provide the amplified data on a data line and a complementary data line. An active load circuit includes a first load device electrically connected between the data line and a voltage source wherein an electrical resistance of the first load device is varied responsive to a voltage level of the data line. The active load circuit also includes a second load device electrically connected between the complementary data line and the voltage source wherein an electrical resistance of the second load device is varied responsive to a voltage level of the complementary data line. Related methods are also discussed.

摘要翻译： 集成电路存储器件可以包括具有多个存储单元的存储单元阵列和位线读出放大器，该位线读出放大器被配置为放大来自存储单元阵列的存储单元的一对位线上的数据，并将放大数据提供到 数据线和补充数据线。 有源负载电路包括电连接在数据线和电压源之间的第一负载装置，其中第一负载装置的电阻响应于数据线的电压电平而变化。 有源负载电路还包括电连接在互补数据线和电压源之间的第二负载装置，其中第二负载装置的电阻响应补充数据线的电压电平而变化。 还讨论了相关方法。

公开(公告)号：US06795372B2

公开(公告)日：2004-09-21

申请号：US10389482

申请日：2003-03-14

申请人： Myeong-o Kim ,  Chi-wook Kim ,  Sung-min Seo

发明人： Myeong-o Kim ,  Chi-wook Kim ,  Sung-min Seo

IPC分类号： G11C800

CPC分类号： G11C7/18 ,  G11C7/065 ,  G11C2207/065

摘要： Bit line sense amplifier driving control circuits and methods for synchronous DRAMs selectively supply and suspend supply of operating voltages for bit line sense amplifiers. More specifically, a synchronous DRAM includes a memory cell array including at least a first column block and a second column block that are divided according to column address, first bit line sense amplifiers that are configured to sense data that is output from the first column block of the memory cell array, and second bit line sense amplifiers that are configured to sense data that is output from the second column block of the memory cell array. A bit line sense amplifier driving control circuit or method is responsive to a row address select signal, to supply an operating voltage to the first and second bit line sense amplifiers, and is responsive to a column select signal that selects a column address in the first column block, to suspend supplying an operating voltage to the second bit line sense amplifiers.

摘要翻译： 用于同步DRAM的位线读出放大器驱动控制电路和方法选择性地供给和暂停供给位线读出放大器的工作电压。 更具体地，同步DRAM包括存储单元阵列，该存储单元阵列至少包括根据列地址划分的第一列块和第二列块，第一位线读出放大器被配置为感测从第一列块输出的数据 以及被配置为感测从存储单元阵列的第二列块输出的数据的第二位线读出放大器。 位线读出放大器驱动控制电路或方法响应于行地址选择信号，向第一和第二位线读出放大器提供工作电压，并响应列选择信号，该列选择信号选择第一位 列块，以暂停向第二位线读出放大器提供工作电压。